intersil EL7156 DATA SHEET

®

www.BDTIC.com/Intersil

EL7156

Data Sheet May 2, 2007

High Performance Pin Driver

The EL7156 high performance pin driver with three-state is
suited to many ATE and level-shifting applications. The 3.5A
peak drive capability makes this part an excellent choice
when driving high capacitance loads.

The output pin OUT is connected to input pins VH or VL
respectively, depending on the status of the IN pin. When the
OE pin is active low, the output is placed in the three-state
mode. The isolation of the output FETs from the power
supplies enables VH and VL to be set independently,
enabling level-shifting to be implemented. Related to the
EL7155, the EL7156 adds a lower supply pin VS- and makes
VL an isolated and independent input. This feature adds
applications flexibility and improves switching response due
to the increased enhancement of the output FETs.

This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and ON-resistance characteristics.

Available in the 8 Ld SOIC and 8 Ld PDIP packages, the
EL7156 is specified for operation over the full -40°C to
+85°C temperature range.

Pinout

EL7156

(8 LD PDIP, SOIC)

TOP VIEW

VS+

OE

GND

1

L
O

2

G

IN

I

3

C

4

8

VH

OUT

7

VL

6

VS-

5

FN7280.3

Features

• Clocking speeds up to 40MHz

• 15ns t

at 2000pF C

R/tF

LOAD

• 0.5ns rise and fall times mismatch

• 0.5ns t

ON-tOFF

prop delay mismatch

• 3.5pF typical input capacitance

• 3.5A peak drive

• Low ON-resistance of 3.5Ω

• High capacitive drive capability

• Operates from 4.5V to 16.5V

• Pb-free plus anneal available (RoHS compliant)

Applications

• ATE/burn-in testers

• Level shifting

•IGBT drivers

• CCD drivers

Ordering Information

PART

PART NUMBER

EL7156CN EL7156CN - 8 Ld PDIP MDP0031
EL7156CNZ

(Note)
EL7156CS 7156CS - 8 Ld SOIC MDP0027
EL7156CS-T7 7156CS 7” 8 Ld SOIC MDP0027
EL7156CS-T13 7156CS 13” 8 Ld SOIC MDP0027
EL7156CSZ

(Note)
EL7156CSZ-T7

(Note)
EL7156CSZ-T13

(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

MARKING

EL7156CN Z - 8 Ld PDIP*

7156CSZ - 8 Ld SOIC

7156CSZ 7” 8 Ld SOIC

7156CSZ 13” 8 Ld SOIC

TA PE &

REEL PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

MDP0031

MDP0027

MDP0027

MDP0027

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

EL7156

www.BDTIC.com/Intersil

Absolute Maximum Ratings (T

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

OUTPUT

R

OVH

R

OVL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

I

VH

SWITCHING CHARACTERISTICS

t

R

t

F

t

RFΔ

t

d-1

t

d-2

t

dΔ

t

d-3

t

d-4

Logic ‘1’ Input Voltage 2.4 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ

ON-Resistance VH to OUT I
ON-Resistance VL to OUT I
Output Leakage Current OE = 0V, OUT = VH/V
Peak Output Current

(linear resistive operation)

Continuous Output Current Source/Sink 200 mA

Power Supply Current Inputs = VS+1.33mA
Off Leakage at VH and V

Rise Time CL = 2000pF 14.5 ns
Fall Time CL = 2000pF 15 ns
tR, tF Mismatch CL = 2000pF 0.5 ns
Tur n-Off Delay Time CL = 2000pF 9.5 ns
Turn-On Delay Time CL = 2000pF 10 ns
t

Mismatch CL = 2000pF 0.5 ns

d-1-td-2

Three-state Delay Enable 10 ns
Three-state Delay Disable 10 ns

= +25°C) Thermal Information

A

- -0.3V, VS +0.3V

S

= TC = T

J

+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified.

S

OUT
OUT

Source 3.5 A
Sink 3.5 A

L

VH, VL = 0V 4 1 0 µA

A

= -200 mA 2.7 4.5 Ω
= +200 mA 3.5 5.5 Ω

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

L

0.1 10 µA

2

FN7280.3

May 2, 2007

EL7156

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

OUTPUT

R

OVH

R

OVL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

V

H

SWITCHING CHARACTERISTICS

t

R

t

F

t

RFΔ

t

d-1

t

d-2

t

dΔ

t

d-3

t

d-4

Logic ‘1’ Input Voltage 2.0 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ

ON-Resistance VH to OUT I
ON-Resistance VL to OUT I
Output Leakage Current OE = 0V, OUT = VH/V
Peak Output Current

(linear resistive operation)

Continuous Output Current Source/Sink 200 mA

Power Supply Current Inputs = VS+12.5mA
Off Leakage at VH and V

Rise Time CL = 2000pF 17 ns
Fall Time CL = 2000pF 17 ns
tR, tF Mismatch CL = 2000pF 0 ns
Turn-Off Delay Time CL = 2000pF 11.5 ns
Turn-On Delay Time CL = 2000pF 12 ns
t

Mismatch CL = 2000pF 0.5 ns

d-1-td-2

Three-state Delay Enable 10 ns
Three-state Delay Disable 10 ns

+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25°C, unless otherwise specified. (Continued)

S

= -200mA 3.4 5 Ω

OUT

= +200mA 4 6 Ω

OUT

L

Source 3.5 A
Sink 3.5 A

L

VH, VL = 0V 4 10 µA

0.1 10 µA

3

FN7280.3

May 2, 2007

Typical Performance Curves

www.BDTIC.com/Intersil

EL7156

JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD

θ

JA

= 100°C/W

85

MAX TJ = +125°C

125 150

1.0

PDIP8

0.8

0.6
SOIC8

0.4

θ

= 160°C/W

0.2

POWER DISSIPATION (W)

0

JA

25 10075050

AMBIENT TEMPERATURE (°C)

FIGURE 1. PACKAGE POWER DISSIP A TION vs AMBIENT

TEMPERATURE

T = +25°C

2.0

1.6

1.2
ALL INPUTS = GND

0.8

SUPPLY CURRENT (mA)

0.4

ALL INPUTS = VS+

T = +25°C

1.8

HIGH THRESHOLD

HYSTERESIS

LOW THRESHOLD

15510

SUPPLY VOLTAGE (V)

INPUT VOLTAGE (V)

1.6

1.4

1.2

1.0

FIGURE 2. INPUT THRESHOLD vs SUPPLY VOLTAGE

I

= 200mA, T = +25°C, VS+ = VH, VS- = VL = 0V

OUT

6

V

- V

OUT

5

4

V

- V

OUT

3

2

“ON” RESISTANCE (Ω)

1

H

L

0

5

SUPPLY VOLTAGE (V)

10

15

FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

CL = 2000pF, T = +25°C

30

25

t

R

RISE/FALL TIME (ns)

20

t

15

10

F

510

SUPPLY VOLTAGE (V)

t

R

t

I

15

FIGURE 5. RISE/FALL TIME vs SUPPLY VOLTAGE

0

7.5 1512.5510

SUPPLY VOLTAGE (V)

FIGURE 4. “ON”-RESISTANCE vs SUPPLY VOLTAGE

CL = 2000pF, VS+ = 15V

20

18

t

F

16

14

t

RISE/FALL TIME (ns)

12

10

-50

0

TEMPERATURE (°C)

R

50

100

FIGURE 6. RISE/FALL TIME vs TEMPERATURE

150

4

FN7280.3

May 2, 2007

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

EL7156

CL = 2000pF, T = +25°C

17

DELAY TIME (ns)

15

13

t

11

9

d-1

5

SUPPLY VOLTAGE (V)

t

d-2

10

15

FIGURE 7. PROPAGATION DELAY vs SUPPLY VOLTAGE

VS+ = +15V, T = +25°C

70

60

50

40

t

30

20

RISE/FALL TIME (ns)

10

F

t

R

CL = 2000pF, VS+ = 15V

14

12

10

DELAY TIME (ns)

8

6

-25 25 75 100

t

d-2

0125-50 50

TEMPERATURE (°C)

t

d-1

FIGURE 8. PROPAGATION DELAY vs TEMPERATURE

+ = VH = 15V, VS- = VL = 0V, T = +25°C, f = 20kHz

V

S

5

4

3

2

1

SUPPLY CURRENT (mA)

0

100 1000

LOAD CAPACITANCE (pF)

10000

FIGURE 9. RISE/FALL TIME vs LOAD CAPACITANCE

+ = VH, VS -= VL = 0V, CL = 0pF

V

S

14

12

10

8

6

4

SUPPLY CURRENT (mA)

2

0

1M 8M6M2M

VS+ = VH = 15V

FREQUENCY (Hz)

VS+ = VH = 10V

VS+=VH

VS+ = VH = 5V

7M 10M1M 4M

9M6M3M

FIGURE 11. SUPPLY CURRENT vs FREQUENCY

0

100 1000 10000

LOAD CAPACITANCE (pF)

FIGURE 10. SUPPLY CURRENT vs LOAD CAPACITANCE

+ = VH, VS- = VL = 0V, CL = 0pF

V

S

30

25

20

15

(mA)

VH

I

10

5

0

1M 8M6M2M

FIGURE 12. V

VS+ = VH = 15V

FREQUENCY (Hz)

SUPPLY CURRENT vs FREQUENCY

H

VS+ = VH = 10V

VS+=VH

VS+ = VH = 5V

7M 10M1M 4M

9M6M3M

5

FN7280.3

May 2, 2007

EL7156

www.BDTIC.com/Intersil

Truth Table

OE IN OUT

0 0 Three-state
0 1 Three-state
10V
11V

Timing Diagram

INPUT

INVERTED

OUTPUT

2.5V

0

90%

10%

5V

Operating Voltage Range

PIN MIN MAX

- to GND -5 0

V

S

+ to VS- 5 16.5

V

S

to V

H
L

V

H

L

+ to V

V

S

H

+ to GND 5 16.5

V

S

VL to VS- 0 16.5

Three-state Output V

t

d1

t

d2

0 16.5
0 16.5

L

V

H

Standard Test Configuration

+

V

S

VS+

10kΩ

0.1µF4.7µF

OE

GND

t

F

1

L

O

2

G

I

IN

3

C

4

EL7156

8

7

6

5

t

R

0.1µF 4.7µF

2000pF

0.1µF 4.7µF

0.1µF 4.7µF

V

H

OUT

V

-

-

L

VS-

6

FN7280.3

May 2, 2007

EL7156

www.BDTIC.com/Intersil

Pin Descriptions

PIN NAME FUNCTION EQUIVALENT CIRCUIT

1 VS+ Positive Supply Voltage
2 OE Output Enable

INPUT

3 IN Input Reference Circuit 1
4 GND Ground
5 VS- Negative Supply Voltage
6 VL Lower Output Voltage
7OUTOutput

VS+

V

VS-

-

S

CIRCUIT 1

V

H

+

V

S

8 VH High Output Voltage

Block Diagram

VS+

GND

V

OUT

V

-

S

VS-

V

CIRCUIT 2

OE

IN

LEVEL

SHIFTER

THREE-

STATE

CONTROL

V

H

OUT

L

-

V

S

7

V

L

FN7280.3

May 2, 2007

EL7156

www.BDTIC.com/Intersil

Applications Information

Product Description

The EL7156 is a high performance 40MHz pin driver. It
contains two analog switches connecting VH and VL to OUT .
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.

Due to the topology of t he EL7156, both the VH and VL pins
can be connected to any voltage between the VS+ and VS­pins, but VH must be greater than VL in order to prevent
turning on the body diode at the output stage.

The EL7156 is available in both the 8 Ld SOIC and the 8 Ld
PDIP packages. The relevant package should be chosen
depending on the calculated power dissipation.

Three-state Operation

When the OE pin is low, the output is three-state (floating).
The output voltage is the parasitic capacitance’s voltage. It
can be any voltage between VH and VL, depending on the
previous state. At three-state, the output voltage can be
pushed to any voltage between VH and VL. The output
voltage can’t be pushed higher than VH or lower than VL
since the body diode at the output stage will turn on.

Supply Voltage Ra nge and Input Compatibility

The EL7156 is designed for operation on supplies from 5V to
15V (4.5V to 16.5V maximum). “Operating Voltage Range”
on page 6 shows the specifications for the relationship
between the VS+, VS-, VH, VL, and GND pins.

All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V
also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7156, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7156 necessitate the use of a bypass
capacitor between the supplies (VS+ and VS-) and GND
pins. It is recommended that a 2.2µF tantalum capacitor be
used in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
pins as possible. It is also recommended that the VH and VL
pins have some level of bypassing, especially if the EL7156
is driving highly capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the
EL7156 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation, die temperature must be kept below
T

(+125°C). It is necessary to calculate the power

JMAX

dissipation for a given application prior to selecting the
package type.

+) of 5V, the EL7156 is

S

Power dissipation may be calculated:

PD VS( IS) CVS( V

S

2

f) C

+()V

INTCL

OUT

2

f××[]+××+×=

(EQ. 1)

where:

V

is the total power supply to the EL7156 (from VS+ to

S

GND)
V

is the swing on the output (VH to VL)

OUT

is the integral capacitance due to VS+

C

VS

is the integral load capacitance due to V

C

INT

H

IS is the quiescent supply current (3mA max)
f is frequency

TABLE 1. INTEGRAL CAPACITANCE

+ = VH(V) CVS(pF) C

V

S

5 80 120
10 85 145
15 90 180

INT

(pF)

Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below T

T

–

JMAXTMAX

-----------------------------------------

=

θ

JA

PD

JMAX

:

(EQ. 2)

where:

T

is the maximum junction temperature (+125°C)

JMAX

is the maximum operating temperature

T

MAX

PD is the power dissipation calculated above

thermal resistance on junction to ambient

θ

JA

is 160°C/W for the SOIC8 package and 100°C/W for the

θ

JA

PDIP8 package when using a standard JEDEC JESD51-3
single-layer test board. If T

is greater than +125°C

JMAX

when calculated using Equation 2, then one of the following
actions must be taken:

Reduce θ

the system by designing more heat-sinking

JA

into the PCB (as compared to the standard JEDEC
JESD51-3).

Use the PDIP8 instead of the SOIC8 package.
De-rate the application either by reducing the switching

frequency, the capacitive load, or the maximum operating
(ambient) temperature (T

MAX

).

8

FN7280.3

May 2, 2007

Plastic Dual-In-Line Packages (PDIP)

www.BDTIC.com/Intersil

EL7156

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

E

eA

eB

N

PIN #1

E1

INDEX

12 N/2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20

b2

Rev. C 2/07

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

9

FN7280.3

May 2, 2007

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

EL7156

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

SYMBOL

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

TOLERANCE NOTESSO-8 SO-14

A

0.010

Rev. M 2/07

10

FN7280.3

May 2, 2007