®
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EL7155
Data Sheet March 9, 2006
High Performance Pin Driver
The EL7155 high performance pin driver with 3-state is
suited to many ATE and level-shifting applications. The 3.5A
peak drive capability makes this part an excellent choice
when driving high capacitance loads.
Output pins OUT
and V
respectively, depending on the status of the IN pin.
L
and OUTL are connected to input pins VH
H
One of the output pins is always in tri-state, except when the
OE pin is active low, in which case both outputs are in
3-state mode. The isolation of the output FETs from the
power supplies enables V
and VL to be set independently,
H
enabling level-shifting to be implemented.
This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and on-resistance characteristics.
Available in 8 Ld SO and 8 Ld PDIP packages, the EL7155
is specified for operation over the full -40°C to +85°C
temperature range.
Pinout
EL7155
(8 LD PDIP, SO)
TOP VIEW
VS+
OE
GND
1
L
o
2
g
i
IN
c
3
4
VH
8
OUTH
7
OUTL
6
VL
5
FN7279.2
Features
• Clocking speeds up to 40MHz
• 15ns tr/tf at 2000pF C
LOAD
• 0.5ns rise and fall times mismatch
• 0.5ns T
ON-TOFF
prop delay mismatch
• 3.5pF typical input capacitance
• 3.5A peak drive
• Low on resistance of 3.5Ω
• High capacitive drive capability
• Operates from 4.5V up to 16.5V
• Pb-free plus anneal available (RoHS compliant)
Applications
• ATE/burn-in testers
• Level shifting
•IGBT drivers
• CCD drivers
Ordering Information
PAR T
PART NUMBER
EL7155CN EL7155CN - 8 Ld PDIP MDP0031
EL7155CS 7155CS - 8 Ld SO MDP0027
EL7155CS-T7 7155CS 7” 8 Ld SO MDP0027
EL7155CS-T13 7155CS 13” 8 Ld SO MDP0027
EL7155CSZ
(Note)
EL7155CSZ-T7
(Note)
EL7155CSZ-T13
(Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
MARKING
7155CSZ - 8 Ld SO
7155CSZ 7” 8 Ld SO
7155CSZ 13” 8 Ld SO
TAPE &
REEL PACKAGE
(Pb-free)
(Pb-free)
(Pb-free)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7155
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Absolute Maximum Ratings (T
Supply Voltage (V
V
, VH to GND, VS+ to VH. . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
H-VL
Input Voltage . . . . . . . . . . . . . . . -0.3V below V
+ to VL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V
S
= 25°C)
A
to +0.3V above V
L
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
S
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
Electrical Specifications V
+ = +15V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified.
S
= TC = T
J
A
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
INPUT
V
IH
I
IH
V
IL
I
IL
C
IN
R
IN
Logic ‘1’ Input Voltage 2.4 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ
OUTPUT
R
R
I
OUT
I
PK
I
DC
OVH
OVL
ON Resistance VH to OUT
ON Resistance VL to OUT
H
L
Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+0.110µA
Peak Output Current
(linear resistive operation)
Continuous Output Current Source/Sink 200 mA
I
= -200mA 2.7 4.5 Ω
OUT
I
= +200mA 3.5 5.5 Ω
OUT
Source 3.5 A
Sink 3.5 A
POWER SUPPLY
I
S
I
VH
Power Supply Current Inputs = VS+1.33mA
Off Leakage at V
H
VH = 0V 4 10 µA
SWITCHING CHARACTERISTICS
t
R
t
F
t
RF∆
t
D-1
t
D-2
t
D∆
t
D-3
t
D-4
Rise Time CL = 2000pF 14.5 ns
Fall Time CL = 2000pF 15 ns
tR, tF Mismatch CL = 2000pF 0.5 ns
Turn-Off Delay Time CL = 2000pF 9.5 ns
Turn-On Delay Time CL = 2000pF 10 ns
t
Mismatch CL = 2000pF 0.5 ns
D-1-tD-2
3-state Delay Enable 10 ns
3-state Delay Disable 10 ns
2
FN7279.2
March 9, 2006
EL7155
www.BDTIC.com/Intersil
Electrical Specifications V
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
INPUT
V
IH
I
IH
V
IL
I
IL
C
IN
R
IN
OUTPUT
R
OVH
R
OVL
I
OUT
I
PK
I
DC
POWER SUPPLY
I
S
I
VH
SWITCHING CHARACTERISTICS
t
R
t
F
t
RF∆
t
D-1
t
D-2
t
D∆
t
D-3
t
D-4
Logic ‘1’ Input Voltage 2.0 V
Logic ‘1’ Input Current VIH = VS+0.110µA
Logic ‘0’ Input Voltage 0.8 V
Logic ‘0’ Input Current VIL = 0V 0.1 10 µA
Input Capacitance 3.5 pF
Input Resistance 50 MΩ
ON Resistance VH to OUT
ON Resistance VL to OUT
Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+0.110µA
Peak Output Current
(linear resistive operation)
Continuous Output Current Source/Sink 200 mA
Power Supply Current Inputs = VS+12.5mA
Off Leakage at V
Rise Time CL = 2000pF 17 ns
Fall Time CL = 2000pF 17 ns
tR, tF Mismatch CL = 2000pF 0 ns
Turn-Off Delay Time CL = 2000pF 11.5 ns
Turn-On Delay Time CL = 2000pF 12 ns
t
3-state Delay Enable 11 ns
3-state Delay Disable 11 ns
Mismatch CL = 2000pF 0.5 ns
D-1-tD-2
+ = +5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.
S
I
H
L
H
= -200mA 3.4 5 Ω
OUT
I
= +200mA 4 6 Ω
OUT
Source 3.5 A
Sink 3.5 A
VH = 0V 4 10 µA
3
FN7279.2
March 9, 2006
Typical Performance Curves
www.BDTIC.com/Intersil
EL7155
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
1
PDIP8
0.8
0.6
SO8
0.4
POWER DISSIPATION (W)
0.2
0
2.0
1.6
1.2
0.8
SUPPLY CURRENT (mA)
0.4
θJA=160°C/W
25 10075050
AMBIENT TEMPERATURE (°C)
Quiescent Supply Current vs Supply Voltage
T=25°C
ALL INPUTS = GND
θJA=100°C/W
85
ALL INPUTS = VS+
Max TJ=125°C
125 150
Input Threshold vs Supply Voltage
T=25°C
1.8
1.6
1.4
INPUT VOLTAGE (V)
1.2
1.0
“On” Resistance vs Supply Voltage
I
=200mA, T=25°C, VS+=VH, VL=0V
OUT
6
5
4
V
3
2
“ON” RESISTANCE (Ω)
1
OUT-VH
HIGH THRESHOLD
LOW THRESHOLD
SUPPLY VOLTAGE (V)
V
OUT-VL
HYSTERESIS
15510
0
5
Rise/Fall Time vs Supply V oltage
CL=2000pF, T=25°C
30
25
20
RISE/FALL TIME (ns)
15
10
5
SUPPLY VOLTAGE (V)
t
F
SUPPLY VOLTAGE (V)
10
t
R
t
R
10
15
t
I
15
0
Rise/Fall Time vs Temperature
CL=2000pF, VS+=15V
20
18
16
14
RISE/FALL TIME (ns)
12
10
-50
7.5 1512.5510
SUPPLY VOLTAGE (V )
t
F
t
R
0
TEMPERATURE (°C)
50
100
150
4
FN7279.2
March 9, 2006
Typical Performance Curves (Continued)
www.BDTIC.com/Intersil
EL7155
Propagation Delay vs Supply Voltage
CL=2000pF, T=25°C
17
15
13
DELAY TIME (ns)
RISE/FALL TIME (ns)
11
9
70
60
50
40
30
20
10
t
D-1
5
Rise/Fall Time vs Load Capacitance
VS+=+15V, T=25°C
Propagation Delay vs Temperature
CL=2000pF, VS+=15V
14
t
D-2
10 0125-50 50
SUPPLY VOLTAGE (V)
15
t
F
t
R
12
10
DELAY TIME (ns)
8
6
-25 25 75 100
Supply Current vs Load Capacitance
VS+=VH=15V, VL=0V, T=25°C, f=20kHz
5
4
3
2
SUPPLY CURRENT (mA)
1
t
D-2
TEMPERATURE (°C)
t
D-1
0
100
Supply Current vs Frequency
=1000pF, T=25°C
C
L
100
10
1.0
SUPPLY CURRENT (mA)
0.1
1000
LOAD CAPACITANCE (pF)
VS+=15V
VS+=5V
1M 10M10k 100k
FREQUENCY (Hz)
VS+=10V
10000
0
100 1000
LOAD CAPACITANCE (pF)
10000
5
FN7279.2
March 9, 2006
EL7155
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Truth Table
OE IN VH to OUTHOUTL to VS-
0 0 Open Open
0 1 Open Open
1 0 Closed Open
1 1 Open Closed
Timing Diagrams
Inverted
Output
Input
2.5V
0
90%
10%
Operating Voltage Range
PIN MIN (V) MAX (V)
V
L
+ - V
V
S
L
- V
V
H
L
- V
V
S+
H
VS+ - GND 5 16.5
3-State Output V
5V
t
D1
t
F
t
D2
t
R
-5 0
5 16.5
0 16.5
0 16.5
L
V
H
Standard Test Configuration
VS+
VS+
4.7µ 0.1µ
10k
OE
GND
V
1
L
o
2
g
i
c
IN
3
4
EL7155
8
0.1µ 4.7µ
7
6
2000p
5
-
0.1µ 4.7µ
H
OUT
V
L
6
FN7279.2
March 9, 2006
EL7155
www.BDTIC.com/Intersil
Pin Descriptions
Pin Name Function Equivalent Circuit
1 VS+ Positive Supply Voltage
2 OE Output Enable
3 IN Input Reference Circuit 1
4 GND Ground
5 VL Negative Supply Voltage
6 OUTL Lower Switch Output
VS+
INPUT
V
L
Circuit 1
VS+
OUT
L
7 OUTH Upper Switch Output
8 VH Upper Output Voltage
Block Diagram
VS+
IN
GND
Level
Shifter
OE
3-State
Control
V
L
Circuit 2
V
H
V
L
Circuit 3
V
H
OUT
H
OUT
L
VS+
V
OUT
H
L
V
L
7
FN7279.2
March 9, 2006
EL7155
www.BDTIC.com/Intersil
Applications Information
Product Description
The EL7155 is a high performance 40MHz pin driver. It
contains two analog switches connecting V
V
to OUTL. Depending on the value of the IN pin, one of the
L
two switches will be closed and the other switch open. An
output enable (OE) is also supplied which opens both
switches simultaneously.
Due to the topology of the EL7155, V
connected to a voltage equal to, or lower than GND. V
be connected to any voltage between V
supply, V
+.
S
The EL7155 is available in both the 8 Ld SO and the 8 Ld
PDIP packages. The relevant package should be chosen
depending on the calculated power dissipation.
3-state Operation
When the OE pin is low, the output is 3-state (floating.) The
output voltage is the parasitic capacitance’s voltage. It can
be any voltage between V
and VL, depending on the
H
previous state. At 3-state, the output voltage can be pushed
to any voltage between V
be pushed higher than V
and VL. The output voltage can’t
H
or lower than VL since the body
H
diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7155 is designed for operation on supplies from 5V to
15V (4.5V to 16.5V maximum). The table on page 6 shows
the specifications for the relationship between the V
V
, and GND pins.
L
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V
+) of 5V, the EL7155 is
S
also compatible with TTL inputs.
Power Supply Bypassing
When using the EL7155, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7155 necessitate the use of a bypass
capacitor between the V
recommended that a 2.2µF tantalum capacitor be used in
parallel with a 0.1µF low-inductance ceramic MLC capacitor.
These should be placed as close to the supply pins as
possible. It is also recommended that the V
have some level of bypassing, especially if the EL7155 is
driving highly capacitive loads.
+ and GND pins. It is
S
to OUTH and
H
should always be
L
and the positive
L
S
and VL pins
H
can
H
+, VH,
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7155 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
T
(125°C). It is necessary to calculate the power
JMAX
dissipation for a given application prior to selecting the
package type.
Power dissipation may be calculated:
PD VS( IS) C
( V
INT
2
S
f ) CL( V
where:
V
is the total power supply to the EL7155 (from VS+ to
S
GND)
V
is the swing on the outp u t (VH - VL)
OUT
is the load capacitance
C
L
is the internal load capacitance (100pF max)
C
INT
is the quiescent supply current (3mA max)
I
S
f is frequency
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below T
T
θ
JA
( T
JMAX
----------------------------------------------=
PD
MAX
)–
where:
T
is the maximum junction temperature (125°C)
JMAX
is the maximum operating temperature
T
MAX
PD is the power dissipa ti o n calculated above
thermal resistance on junction to ambient
θ
JA
is 160°C/W for the SO8 package and 100°C/W for the
θ
JA
PDIP8 package when using a standard JEDEC JESD51-3
single-layer test board. If T
is greater than 125°C when
JMAX
calculated using the equation above, then one of the
following actions must be taken:
Reduce θ
the system by designing more heat-sinking
JA
into the PCB (as compared to the standard JEDEC
JESD51-3)
Use the PDIP8 instead of the SO8 package
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (T
MAX
)
OUT
2
f )××+××+×=
JMAX
:
8
FN7279.2
March 9, 2006
EL7155
www.BDTIC.com/Intersil
9
FN7279.2
March 9, 2006
EL7155
www.BDTIC.com/Intersil
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7279.2
March 9, 2006
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