intersil EL7155 DATA SHEET

®

www.BDTIC.com/Intersil

EL7155

Data Sheet March 9, 2006

High Performance Pin Driver

The EL7155 high performance pin driver with 3-state is
suited to many ATE and level-shifting applications. The 3.5A
peak drive capability makes this part an excellent choice
when driving high capacitance loads.

Output pins OUT
and V

respectively, depending on the status of the IN pin.

L

and OUTL are connected to input pins VH

H

One of the output pins is always in tri-state, except when the
OE pin is active low, in which case both outputs are in
3-state mode. The isolation of the output FETs from the
power supplies enables V

and VL to be set independently,

H

enabling level-shifting to be implemented.

This pin driver has improved performance over existing pin
drivers. It is specifically designed to operate at voltages
down to 0V across the switch elements while maintaining
good speed and on-resistance characteristics.

Available in 8 Ld SO and 8 Ld PDIP packages, the EL7155
is specified for operation over the full -40°C to +85°C
temperature range.

Pinout

EL7155

(8 LD PDIP, SO)

TOP VIEW

VS+

OE

GND

1

L
o

2

g

i

IN

c

3

4

VH

8

OUTH

7

OUTL

6

VL

5

FN7279.2

Features

• Clocking speeds up to 40MHz

• 15ns tr/tf at 2000pF C

LOAD

• 0.5ns rise and fall times mismatch

• 0.5ns T

ON-TOFF

prop delay mismatch

• 3.5pF typical input capacitance

• 3.5A peak drive

• Low on resistance of 3.5Ω

• High capacitive drive capability

• Operates from 4.5V up to 16.5V

• Pb-free plus anneal available (RoHS compliant)

Applications

• ATE/burn-in testers

• Level shifting

•IGBT drivers

• CCD drivers

Ordering Information

PAR T

PART NUMBER

EL7155CN EL7155CN - 8 Ld PDIP MDP0031

EL7155CS 7155CS - 8 Ld SO MDP0027

EL7155CS-T7 7155CS 7” 8 Ld SO MDP0027

EL7155CS-T13 7155CS 13” 8 Ld SO MDP0027

EL7155CSZ
(Note)

EL7155CSZ-T7
(Note)

EL7155CSZ-T13
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

7155CSZ - 8 Ld SO

7155CSZ 7” 8 Ld SO

7155CSZ 13” 8 Ld SO

TAPE &

REEL PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

MDP0027

MDP0027

MDP0027

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

EL7155

www.BDTIC.com/Intersil

Absolute Maximum Ratings (T

Supply Voltage (V
V

, VH to GND, VS+ to VH. . . . . . . . . . . . . . . . . . . . . . . . . 16.5V

H-VL

Input Voltage . . . . . . . . . . . . . . . -0.3V below V

+ to VL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V

S

= 25°C)

A

to +0.3V above V

L

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C

S

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

+ = +15V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified.

S

= TC = T

J

A

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

Logic ‘1’ Input Voltage 2.4 V

Logic ‘1’ Input Current VIH = VS+0.110µA

Logic ‘0’ Input Voltage 0.8 V

Logic ‘0’ Input Current VIL = 0V 0.1 10 µA

Input Capacitance 3.5 pF

Input Resistance 50 MΩ

OUTPUT

R

R

I

OUT

I

PK

I

DC

OVH

OVL

ON Resistance VH to OUT

ON Resistance VL to OUT

H

L

Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+0.110µA

Peak Output Current
(linear resistive operation)

Continuous Output Current Source/Sink 200 mA

I

= -200mA 2.7 4.5 Ω

OUT

I

= +200mA 3.5 5.5 Ω

OUT

Source 3.5 A

Sink 3.5 A

POWER SUPPLY

I

S

I

VH

Power Supply Current Inputs = VS+1.33mA

Off Leakage at V

H

VH = 0V 4 10 µA

SWITCHING CHARACTERISTICS

t

R

t

F

t

RF∆

t

D-1

t

D-2

t

D∆

t

D-3

t

D-4

Rise Time CL = 2000pF 14.5 ns

Fall Time CL = 2000pF 15 ns

tR, tF Mismatch CL = 2000pF 0.5 ns

Turn-Off Delay Time CL = 2000pF 9.5 ns

Turn-On Delay Time CL = 2000pF 10 ns

t

Mismatch CL = 2000pF 0.5 ns

D-1-tD-2

3-state Delay Enable 10 ns

3-state Delay Disable 10 ns

2

FN7279.2

March 9, 2006

EL7155

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

C

IN

R

IN

OUTPUT

R

OVH

R

OVL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

I

VH

SWITCHING CHARACTERISTICS

t

R

t

F

t

RF∆

t

D-1

t

D-2

t

D∆

t

D-3

t

D-4

Logic ‘1’ Input Voltage 2.0 V

Logic ‘1’ Input Current VIH = VS+0.110µA

Logic ‘0’ Input Voltage 0.8 V

Logic ‘0’ Input Current VIL = 0V 0.1 10 µA

Input Capacitance 3.5 pF

Input Resistance 50 MΩ

ON Resistance VH to OUT

ON Resistance VL to OUT

Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+0.110µA

Peak Output Current
(linear resistive operation)

Continuous Output Current Source/Sink 200 mA

Power Supply Current Inputs = VS+12.5mA

Off Leakage at V

Rise Time CL = 2000pF 17 ns

Fall Time CL = 2000pF 17 ns

tR, tF Mismatch CL = 2000pF 0 ns

Turn-Off Delay Time CL = 2000pF 11.5 ns

Turn-On Delay Time CL = 2000pF 12 ns

t

3-state Delay Enable 11 ns

3-state Delay Disable 11 ns

Mismatch CL = 2000pF 0.5 ns

D-1-tD-2

+ = +5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.

S

I

H

L

H

= -200mA 3.4 5 Ω

OUT

I

= +200mA 4 6 Ω

OUT

Source 3.5 A

Sink 3.5 A

VH = 0V 4 10 µA

3

FN7279.2

March 9, 2006