intersil EL7154 DATA SHEET

®

www.BDTIC.com/Intersil

EL7154

Data Sheet March 8, 2007

High Speed, Monolithic Pin Driver

The EL7154 three-state pin driver is particularly well suited
for ATE and level shifting applications. The 4A peak drive
capability, makes the EL7154 an excellent choice when
driving high speed capacitive lines.

The P-Channel MOSFET is completely isolated from the
power supply, providing a high degree of flexibility. Pin (7)
can be grounded, and the output can be taken from pin (8)
when a “source follower” output is desired. The N-Channel
MOSFET has an isolated drain, but shares a common bus
with pre-drivers and level shifter circuits. This is necessary to
ensure that the N-Channel device can turn off effectively
when V

goes below GND. In some power-FET and IGBT

L

applications, negative drive is desirable to insure effective
turn-off. The EL7154 can be used in these applications by
returning V

to a moderate negative potential.

L

Pinout

EL7154

(8 LD PDIP, 8 LD SOIC)

TOP VIEW

VDD

1

THREE-STATE

2

3

INPUT

LEVEL

SHIFT

AND

LOGIC

VL

VH

8

POUT

7

6

NOUT

FN7278.2

Features

• Comparatively low cost

• Three-State output

• 3V and 5V Input compatible

• Clocking speeds up to 10MHz

• 20ns Switching/delay time

• 4A Peak drive

• Isolated drains

• Low output impedance: 2.5Ω

• Low quiescent current: 5mA

• Wide operating voltage: 4.5V to16V

• Isolated P-Channel device

• Separate ground and V

pins

L

• Pb-free plus anneal available (RoHS compliant)

Applications

• Loaded circuit board testers

• Digital testers

• Level shifting below GND

•IGBT drivers

• CCD drivers

45

GND VL

VL

Truth T able

THREE-STATE INPUT P

0 0 Open Open
0 1 Open Open
1 0 HIGH Open
1 1 Open LOW

Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047,
#5,352,578, #5,352,389, #5,351,012, #5,374,898

OUT

1

N

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Ordering Information

www.BDTIC.com/Intersil

EL7154

PART

NUMBER

EL7154CN EL7154CN - 8 Ld PDIP MDP0031
EL7154CNZ EL7154CN Z - 8 Ld PDIP*

EL7154CS 7154CS - 8 Ld SOIC MDP0027
EL7154CS-T7 7154CS 7” 8 Ld SOIC MDP0027
EL7154CS-T13 7154CS 13” 8 Ld SOIC MDP0027
EL7154CSZ

(See Note)
EL7154CSZ-T7

(See Note)
EL7154CSZ-T13

(See Note)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

7154CSZ - 8 Ld SOIC

7154CSZ 7” 8 Ld SOIC

7154CSZ 13” 8 Ld SOIC

PART

MARKING

TAPE AND

REEL PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

MDP0031

MDP0027

MDP0027

MDP0027

Nominal Operating Voltage Range

PIN MIN MAX

V

L

to V

V

DD

to V

V

H

VDD to V
V

DD

L

L

H

-3 0
515
215

-0.5 15
515

2

FN7278.2

March 8, 2007

EL7154

www.BDTIC.com/Intersil

Absolute Maximum Ratings (T

Supply (VDD to VL; VH to VL, VH to GND),
V+ to V
V

Input Pins. . . . . . . . . . . . . . . . . -0.3V below V

Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V

H

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V

L

= +25°C) Thermal Information

A

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C

to +0.3V above V

L

DD

Power Dissipation

SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW

PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T

DC Electrical Specifications T

= +25°C, VDD = +12V, VH = +12V, VL = -3V, unless otherwise specified.

A

= TC = T

J

A

PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS

INPUT

V
I
V
I
V

IH

IH

IL

IL

HVS

Logic “1” Input Voltage 2.4 V
Logic “1” Input Current VIH = V

DD

0.1 10 µA
Logic “0” Input Voltage 0.6 V
Logic “0” Input Current VIL = 0V 0.1 10 µA
Input Hysteresis 0.3 V

OUTPUT

R
R
I

OUT

I

PK

I

DC

OH
OL

Pull-Up Resistance I
Pull-Down Resistance I
Output Leakage Current VDD/GND 0.2 10 µA
Peak Output Current Source/Sink 4.0 A
Continuous Output Current Source/Sink 200 mA

= -100mA 1.5 4 Ω

OUT

= +100mA 2 4 Ω

OUT

POWER SUPPLY

I

S

V

S

I

G

I

H

Power Supply Current Inputs = V

DD

Operating Voltage 4.5 16 V
Current to GND (Pin 4) 1 10 µA
Off Leakage at V

H

Pin 8 = 0V 1 10 µA

12.5mA

AC Electrical Specifications T

= +25°C unless otherwise specified

A

PARAMETER DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING CHARACTERISTICS (V

t

t

t
t
t
t

R

F

D-1
D-2
D-1
D-2

Rise Time CL = 100pF 4 25 ns

Fall Time CL = 100pF 4 25 ns

Turn-Off Delay Time CL = 2000pF 20 25 ns
Turn-On Delay Time CL = 2000pF 10 25 ns
Three-State Delay 25 ns
Three-State Delay 25 ns

= VH = 12V; VL = -3V)

DD

= 2000pF 20

C

L

= 2000pF 20

C

L

3

FN7278.2

March 8, 2007

Timing Table

www.BDTIC.com/Intersil

Standard Test Configuration

EL7154

4

FN7278.2

March 8, 2007

Typical Performance Curves

www.BDTIC.com/Intersil

EL7154

FIGURE 1. MAX POWER DERATING CURVES

FIGURE 3. INPUT CURRENT vs VOLTAGE

FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE

FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE

FIGURE 5. QUIESCENT SUPPLY CURRENT FIGURE 6. “ON” RESISTANCE vs SUPPLY VOLTAGE

FIGURE 7. AVERAGE SUPPL Y CURRENT vs VOLT AGE AND

FREQUENCY

5

FIGURE 8. RISE/FALL TIME vs LOAD

FN7278.2

March 8, 2007

Typical Applications

www.BDTIC.com/Intersil

EL7154

FIGURE 9. PIN DRIVER

FIGURE 11. IGBT DRIVER WITH NEGATIVE SWING

FIGURE 10. ADJUSTABLE AMPLITUDE PULSE GENERATOR

FIGURE 12. PMDS FOLLOWER

FIGURE 13. RESONANT GATE DRIVER

6

FN7278.2

March 8, 2007

Small Outline Package Family (SO)

www.BDTIC.com/Intersil

A

D

NN

(N/2)+1

EL7154

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

INCHES

SO16

SYMBOL

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

TOLERANCE NOTESSO-8 SO-14

A

0.010

Rev. M 2/07

7

FN7278.2

March 8, 2007

Plastic Dual-In-Line Packages (PDIP)

www.BDTIC.com/Intersil

EL7154

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

E

eA

eB

N

PIN #1

E1

INDEX

12 N/2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

INCHES

SYMBOL

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20

b2

Rev. C 2/07

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

8

FN7278.2

March 8, 2007