intersil EL7104 DATA SHEET

®

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EL7104

Data Sheet July 6, 2006

High Speed, Single Channel, Power
MOSFET Driver

The EL7104 is a matched driver IC that improves the
operation of the industry-standard TC-4420/29 clock drivers.
The Elantec version is a very high speed driver capable of
delivering peak currents of 1A into highly capacitive loads.
The high speed performance is achieved by means of a
proprietary “Turbo-Driver” circuit that speeds up input stages
by tapping the wider voltage swing at the output. Improved
speed and drive capability are enhanced by matched rise
and fall delay times. These matched delays maintain the
integrity of input-to-output pulse-widths to reduce timing
errors and clock skew problems. This improved performance
is accompanied by a 10-fold reduction in supply currents
over bipolar drivers, yet without the delay time problems
commonly associated with CMOS drivers.

The EL7104 is available in 8-pin SO and 8-pin PDIP
packages and is specified for operation over the full -40°C to
+85°C temperature range.

FN7113.2

Features

• Industry-standard driver replacement

• Improved response times

• Matched rise and fall times

• Reduced clock skew

• Low output impedance

• Low input capacitance

• High noise immunity

• Improved clocking rate

• Low supply current

• Wide operating range

• Separate drain connections

• Pb-Free available (RoHS compliant)

Applications

Ordering Information

PART

NUMBER

EL7104CN EL7104CN 8 Ld PDIP - MDP0031
EL7104CNZ EL7104CN Z 8 Ld PDIP* - MDP0031
EL7104CS 7104CS 8 Ld SOIC - MDP0027
EL7104CS-T7 7104CS 8 Ld SOIC 7” MDP0027
EL7104CS-T13 7104CS 8 Ld SOIC 13” MDP0027
EL7104CSZ

(See Note)
EL7104CSZ-T7

(See Note)
EL7104CSZ-T13

(See Note)

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

PART

MARKING PACKAGE

7104CSZ 8 Ld SOIC

(Pb-free)

7104CSZ 8 Ld SOIC

(Pb-free)

7104CSZ 8 Ld SOIC

(Pb-free)

TAPE &

REEL

- MDP0027

7” MDP0027

13” MDP0027

PKG.

DWG. #

• Clock/line drivers

• CCD drivers

• Ultrasound transducer drivers

• Power MOSFET drivers

• Switch mode power supplies

• Resonant charging

• Cascoded drivers

Pinout

EL7104

(8-PIN SO, PDIP)

TOP VIEW

1

V+

2

IN

3

NC

4

GND

8

7

6

5

V+

P_OUT

N_OUT

GND

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

EL7104

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Absolute Maximum Ratings (T

Supply (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V

Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+

Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Ty p values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

DC Electrical Specifications V+

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT

V

IH

I

IH

V

IL

I

IL

V

HVS

OUTPUT

R

OH

R

OL

I

OUT

I

PK

I

DC

POWER SUPPLY

I

S

V

S

Logic “1” Input Voltage 2.4 V
Logic “1” Input Current @V+ 0.1 10 µA
Logic “0” Input Voltage 0.8 V
Logic “0” Input Current @0V 0.1 10 µA
Input Hysteresis 0.3 V

Pull-Up Resistance I
Pull-Down Resistance I
Output Leakage Current V+/GND 0.2 10 µA
Peak Output Current Source/Sink 4.0 A
Continuous Output Current Source/Sink 200 mA

Power Supply Current Input = V+ 4.5 7.5 mA
Operating Voltage 4.5 16 V

= 25°C)

A

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C

Power Dissipation

= TC = T

J

= 15V, TA = 25°C unless otherwise specified.

A

= -100mA 1.5 4 Ω

OUT

= +100mA 2 4 Ω

OUT

SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570mW

PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW

AC Electrical Specifications V

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SWITCHING CHARACTERISTICS (V

t

R

t

F

t

D-ON

t

D-OFF

Rise Time CL = 1000pF 7.5 ns

Fall Time CL = 1000pF 10 ns

Turn-On Delay Time See Timing Table 18 25 ns
Turn-Off Delay Time See Timing Table 18 25 ns

= 15V, TA = 25°C unless otherwise specified.

= VH = 12V; VL = -3V)

DD

= 2000pF 10 20 ns

C

L

= 2000pF 15 20 ns

C

L

2

Timing Table

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EL7104

5V

Input

Inverted

Output

EL7114

Non-inverted

Output

EL7104

Standard Test Configuration

Input

Signal

2.5V

0

90%

10%

90%

10%

t

D1

18

2

D.U.T.

t

F

t

R

6

7

t

D2

4.7µF

Output
Signal

t

R

t

F

Simplified Schematic

45

2000pF

3

Typical Performance Curves

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EL7104

MAX POWER/DERATING CURVES

INPUT CURRENT vs VOLTAGE

SWITCH THRESHOLD vs SUPPLY VOLTAGE

PEAK DRIVE vs SUPPLY VOLTAGE

QUIESCENT SUPPLY CURRENT

“ON” RESISTANCE vs SUPPLY VOLTAGE

4

Typical Performance Curves (Continued)

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EL7104

AVERAGE SUPPLY CURRENT vs
VOLTAGE AND FREQUENCY

RISE/FALL TIME vs SUPPLY VOLTAGE

RISE/FALL TIME vs LOAD

PROPAGATION DELAY vs SUPPLY VOLTAGE

RISE/FALL TIME vs TEMPERATURE

RISE/FALL TIME vs TEMPERATURE

5

Small Outline Package Family (SO)

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A

D

NN

(N/2)+1

EL7104

h X 45°

PIN #1

E

C

SEATING
PLANE

0.004 C

E1

B

0.010 BM CA

I.D. MARK

1

e

0.010 BM CA

(N/2)

c

SEE DETAIL “X”

L1

H

A2

GAUGE
PLANE

A1

b

DETAIL X

L

4° ±4°

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL SO-8 SO-14

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28) TOLERANCE NOTES

A

0.010

Rev. L 2/01

6

Plastic Dual-In-Line Packages (PDIP)

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EL7104

SEATING
PLANE

D

A2

A

L

L

e

b

A1

NOTE 5

c

E

eA

eB

N

PIN #1

E1

INDEX

12 N/2

b2

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

Rev. B 2/99

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s subs idi aries.

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