intersil EL5225 DATA SHEET

®

EL5225

Data Sheet March 11, 2004

10-Channel TFT-LCD Reference Voltage
Generator

The EL5225 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the 3-wire, SPI compatible interface.

A number of the EL5225 can be stacked for applications
requiring more than 10 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.

The EL5225 has 10 outputs, and is available in the 24-pin
TSSOP package. They are specified for operation over the
full -40°C to +85°C temperature range.

Ordering Information

PART

NUMBER

(See Note)

EL5225IRZ 24-Pin TSSOP - MDP0044

EL5225IRZ-T7 24-Pin TSSOP 7” MDP0044

EL5225IRZ-T13 24-Pin TSSOP 13” MDP0044

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

PACKAGE

(Pb-Free)

TAPE &

REEL PKG. DWG. #

Features

• 10-channel reference outputs

• Accuracy of ±1%

• Supply voltage of 5V to 16.5V

• Digital supply 3.3V to 5V

• Low supply current of 9mA

• Rail-to-rail capability

• Pb-free available (RoHS compliant)

Applications

• TFT-LCD drive circuits

• Reference voltage generators

Pinout

EL5225

(24-PIN TSSOP)

TOP VIEW

1

ENA OUTA

2

SDI

3

SCLK

4

SDO

VS+

VSD

REFH

REFL

5

6

7

8

9

EXT_OSC

24

23

22

21

20

19

18

17

16

FN7356.0

OUTB

OUTC

GND

OUTD

OUTE

OUTF

OUTG

GND

10

VS+

11

GND

12

CAP

1

Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

15

14

13

OUTH

OUTI

OUTJ

EL5225

Absolute Maximum Ratings (T

Supply Voltage between V
Supply Voltage between V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

& GND. . . . . . . . 4.5V (min) to 18V (max)

S

& GND . . 3V (min) to VS and 7V (max)

SD

= 25°C)

A

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= 15V, V

S

otherwise specified.

SD

= TC = T

J

= 5V, V

REFH

A

= 13V, V

= 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = 25°C, unless

REFL

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY

I

S

I

SD

Supply Current No load 9 11.5 mA

Digital Supply Current 0.17 0.35 mA

ANALOG

V

OL

V

OH

I

SC

PSRR Power Supply Rejection Ratio V

t

D

V

AC

∆V

MIS

V

DROOP

R

INH

REG Load Regulation I

Output Swing Low Sinking 5mA (V

Output Swing High Sourcing 5mA (V

REFH

REFH

= 15V, V

= 15V, V

= 0) 50 150 mV

REFL

= 0) 14.85 14.95 V

REFL

Short Circuit Current RL = 10Ω 100 140 mA

+ is moved from 14V to 16V 45 65 dB

S

Program to Out Delay 4ms

Accuracy referred to the ideal value Code = 512 20 mV

Channel to Channel Mismatch Code = 512 2 mV

Droop Voltage 12mV/ms

Input Resistance @ V

REFH

, V

REFL

32 kΩ

= 5mA step 0.5 1.5 mV/mA

OUT

CAP Band Gap Bypass with 0.1µF 1 1.3 1.6 V

DIGITAL

V

IH

F

CLK

V

IL

t

S

t

H

t

LC

t

CE

t

DCO

R

SDIN

T

PULSE

Logic 1 Input Voltage VSD = 5V 4 V

= 3.3V 2 V

V

SD

Clock Frequency 5MHz

Logic 0 Input Voltage VSD = 3.3V/5V 1 V

Setup Time 20 ns

Hold Time 20 ns

Load to Clock Time 20 ns

Clock to Load Line 20 ns

Clock to Out Delay Time Negative edge of SCLK 10 ns

S

Input Resistance 1GΩ

DIN

Minimum Pulse Width for EXT_OSC

5µs

Signal

Duty Cycle Duty Cycle for EXT_OSC Signal 50 %

INL Integral Nonlinearity Error 1.3 LSB

DNL Differential Nonlinearity Error 0.5 LSB

F_OSC Internal Refresh Oscillator Frequency OSC_Select = 0 21 kHz

2

FN7356.0

March 11, 2004

EL5225

Pin Descriptions

PIN NUMBER PIN NAME PIN TYPE PIN FUNCTION

1ENA

2 SDI Logic Input Serial data input

3 SCLK Logic Input Serial data clock

4 SDO Logic Output Serial data output

5 EXT_OSC Logic Input/Output External oscillator input or internal oscillator output

6, 10 VS+ Analog Power Positive supply voltage for analog circuits

NC Not connected

7 VSD Digital Power Positive power supply for digital circuits (3.3V - 5V)

8 REFH Analog Reference Input High reference voltage

9 REFL Analog Reference Input Low reference voltage

11 GND Ground Ground

12 CAP Analog Bypass Pin Decoupling capacitor for internal reference generator, 0.1µF

13 OUTJ Analog Output Channel J programmable output voltage

14 OUTI Analog Output Channel I programmable output voltage

Logic Input Chip select, low enables data input to logic

15 OUTH Analog Output Channel H programmable output voltage

17 OUTG Analog Output Channel G programmable output voltage

18 OUTF Analog Output Channel F programmable output voltage

19 OUTE Analog Output Channel E programmable output voltage

20 OUTD Analog Output Channel D programmable output voltage

22 OUTC Analog Output Channel C programmable output voltage

23 OUTB Analog Output Channel B programmable output voltage

24 OUTA Analog Output Channel A programmable output voltage

OUTL Analog Output Channel L programmable output voltage

OUTK Analog Output Channel K programmable output voltage

16, 21 GND Power Ground

3

FN7356.0

March 11, 2004

Typical Performance Curves

EL5225

0.3

0.2

0.1

0

-0.1

-0.2

DIFFERENTIAL NONLINEARITY (LSB)

-0.3
10 210 410 610 810 1010

INPUT CODE

VS=15V

=5V

V

SD

V

REFH

V

REFL

=13V

=2V

1.5

1

0.5

0

INL (LSB)

-0.5

-1
0 200 400 600 800 1200

CODE

REFH=13V
REF

=2V

L

1000

FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE FIGURE 2. INTEGRAL NONLINEARITY ERROR

0mA

5mA

5V

CL=1nF

=20Ω

R

S

CL=4.7nF

=20Ω

R

S

5mA/DIV

200mV/DIV

5mA

0mA

CL=1nF

R

=20Ω

S

CL=4.7nF

R

=20Ω

S

CL=180pF

200mV/DIV

CL=180pF

M=400ns/DIV

VS=V

REFH

=15V

M=400ns/DIV

VS=V

REFH

=15V

FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING) FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)

5V

0V

5V

0V

10V

5V

0V

OUTPUT

M=400µs/DIV

SCLK

SDA

FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V

TO 8V)

5V

0V

5V

0V

10V

5V

0V

OUTPUT

M=400µs/DIV

FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V

TO 0V)

SCLK

SDA

4

FN7356.0

March 11, 2004