intersil EL5120, EL5220, EL5420 DATA SHEET

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EL5120, EL5220, EL5420

Data Sheet February 21, 2005

12MHz Rail-to-Rail Input-Output Op Amps

The EL5120, EL5220, and EL5420 are low power, high
voltage, rail-to-rail input-output amplifiers. The EL5120
contains a single amplifier, the EL5220 contains two
amplifiers, and the EL5420 contains four amplifiers.
Operating on supplies ranging from 5V to 15V, while
consuming only 500µA per amplifier, the EL5120, EL5220,
and EL5420 have a bandwidth of 12MHz (-3dB). They also
provide common mode input ability beyond the supply rails,
as well as rail-to-rail output capability. This enables these
amplifiers to offer maximum dynamic range at any supply
voltage.

The EL5120, EL5220, and EL5420 also feature fast slewing
and settling times, as well as a high output drive capability of
30mA (sink and source). These features make these
amplifiers ideal for use as voltage reference buffers in Thin
Film Transistor Liquid Crystal Displays (TFT-LCD). Other
applications include battery power, portable devices, and
anywhere low power consumption is important.

FN7186.4

Features

• 12MHz -3dB bandwidth

• Supply voltage = 4.5V to 16.5V

• Low supply current (per amplifier) = 500µA

• High slew rate = 10V/µs

• Unity-gain stable

• Beyond the rails input capability

• Rail-to-rail output swing

• Ultra-small package

• Pb-Free available (RoHS compliant)

Applications

• TFT-LCD drive circuits

• Electronics notebooks

• Electronics games

The EL5420 is available in the space-saving 14-pin TSSOP
package, the industry-standard 14-pin SO package, as well
as the 16-pin QFN package. The EL5220 is available in the
8-pin MSOP package and the EL5120 is available in the 5­pin TSOT and 8-pin HMSOP packages. All feature a
standard operational amplifier pin out. These amplifiers are
specified for operation over the full -40°C to +85°C
temperature range.

• Touch-screen displays

• Personal communication devices

• Personal digital assistants (PDA)

• Portable instrumentation

• Sampling ADC amplifiers

• Wireless LANs

• Office automation

• Active filters

• ADC/DAC buffer

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

EL5120, EL5220, EL5420

Ordering Information

PART NUMBER PACKAGE

EL5120IWT-T7 5-Pin TSOT 7” (3K pcs) MDP0049

EL5120IWT-T7A 5-Pin TSOT 7” (250 pcs) MDP0049

EL5120IWTZ-T7
(See Note)

EL5120IWTZ-T7A
(See Note)

5-Pin TSOT

(Pb-Free)

5-Pin TSOT

(Pb-Free)

EL5120IYE 8-Pin HMSOP - MDP0050

EL5120IYE-T7 8-Pin HMSOP 7” MDP0050

EL5120IYE-T13 8-Pin HMSOP 13” MDP0050

EL5120IYEZ
(See Note)

EL5120IYEZ-T7
(See Note)

EL5120IYEZ-T13
(See Note)

8-Pin HMSOP

(Pb-Free)

8-Pin HMSOP

(Pb-Free)

8-Pin HMSOP

(Pb-Free)

EL5220CY 8-Pin MSOP - MDP0043

EL5220CY-T7 8-Pin MSOP 7” MDP0043

EL5220CY-13 8-Pin MSOP 13” MDP0043

EL5220CYZ
(See Note)

EL5220CYZ-T7
(See Note)

EL5220CYZ-T13
(See Note)

8-Pin MSOP

(Pb-Free)

8-Pin MSOP

(Pb-Free)

8-Pin MSOP

(Pb-Free)

EL5420CL 16-Pin QFN - MDP0046

EL5420CL-T7 16-Pin QFN 7” MDP0046

EL5420CL-T13 16-Pin QFN 13” MDP0046

TAPE &

RE E L PK G. D WG. #

7” (3K pcs) MDP0049

7” (250 pcs) MDP0049

- MDP0050

7” MDP0050

13” MDP0050

- MDP0043

7” MDP0043

13” MDP0043

Ordering Information (Continued)

TAPE &

PART NUMBER PACKAGE

EL5420CLZ
(See Note)

EL5420CLZ-T7
(See Note)

EL5420CLZ-T13
(See Note)

16-Pin QFN

(Pb-free)

16-Pin QFN

(Pb-free)

16-Pin QFN

(Pb-free)

EL5420CS 14-Pin SO - MDP0027

EL5420CS-T7 14-Pin SO 7” MDP0027

EL5420CS-T13 14-Pin SO 13” MDP0027

EL5420CSZ
(See Note)

EL5420CSZ-T7
(See Note)

EL5420CSZ-T13
(See Note)

14-Pin SO

(Pb-free)

14-Pin SO

(Pb-free)

14-Pin SO

(Pb-free)

EL5420CR 14-Pin TSSOP - MDP0044

EL5420CR-T7 14-Pin TSSOP 7” MDP0044

EL5420CR-T13 14-Pin TSSOP 13” MDP0044

EL5420CRZ
(Note)

EL5420CRZ-T7
(Note)

EL5420CRZ-T13
(Note)

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

14-Pin TSSOP

(Pb-Free)

14-Pin TSSOP

(Pb-Free)

14-Pin TSSOP

(Pb-Free)

REEL PKG. DWG. #

- MDP0046

7” MDP0046

13” MDP0046

- MDP0027

7” MDP0027

13” MDP0027

- MDP0044

7” MDP0044

13” MDP0044

Pinouts

EL5120

(5-PIN TSOT)

TOP VIEW

1

VOUT VS+

2

VS-

3

5

VS+

-+

4

VIN-VIN+

VOUTA

VINA-

VINA+

EL5120

(8-PIN HMSOP)

TOP VIEW

NC

IN-

IN+

1

2

-

+

3

4

8

NC

VS+

7

OUT

6

NCVS-

5

VOUTA

VINA-

VINA+

VS+

VINB+

VINB-

EL5220

(8-PIN MSOP)

TOP VIEW

1

2

-

+

3

4

EL5420

(14-PIN TSSOP, SO)

TOP VIEW

1

2

-+ -+

3

4

5

-+ -+

6

7

EL5420

(16-PIN QFN)

TOP VIEW

8

7

VOUTB

6

VINB-

-

+

5

VINB+VS-

14

VOUTD

VIND-

13

VIND+

12

VS-

11

VINC+

10

VINC-

9

VOUTCVOUTB

8

VINA-

VINA+

VS+

VINB+

1

2

3

4

NC

VOUTA

16

15

THERMAL

PAD

5

6

VINB-

VOUTB

VOUTD

NC

14

13

12

VIND-

VIND+

11

VS-

10

VINC+

9

7

8

VINC-

VOUTC

2

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Absolute Maximum Ratings (T

Supply Voltage between V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

+ and VS- . . . . . . . . . . . . . . . . . . . .+18V

S

= 25°C)

A

- - 0.5V, VS +0.5V

S

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = 25°C, unless otherwise specified.

S+

= TC = T

J

A

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

V

OS

TCV

I

B

R

IN

C

IN

OS

Input Offset Voltage V

= 0V 2 12 mV

CM

Average Offset Voltage Drift (Note 1) 5 µV/°C

Input Bias Current V

= 0V 2 50 nA

CM

Input Impedance 1GΩ

Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -5.5 +5.5 V

CMRR Common-Mode Rejection Ratio for V

A

VOL

Open Loop Gain -4.5V ≤ V

from -5.5V to +5.5V 50 70 dB

IN

≤ +4.5V 75 95 dB

OUT

OUTPUT CHARACTERISTICS

V

V

I

SC

I

OUT

OL

OH

Output Swing Low IL = -5mA -4.92 -4.85 V

Output Swing High IL = 5mA 4.85 4.92 V

Short Circuit Current ±120 mA

Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio V

I

S

Supply Current (Per Amplifier) No load 500 750 µA

is moved from ±2.25V to ±7.75V 60 80 dB

S

DYNAMIC PERFORMANCE

SR Slew Rate (Note 2) -4.0V ≤ V

t

S

BW -3dB Bandwidth R

GBWP Gain-Bandwidth Product R

PM Phase Margin R

Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

= 10kΩ, CL = 10pF 12 MHz

L

= 10kΩ, CL = 10pF 8 MHz

L

= 10kΩ, CL = 10 pF 50 °

L

≤ +4.0V, 20% to 80% 10 V/µs

OUT

CS Channel Separation f = 5MHz (EL5220 & EL5420 only) 75 dB

NOTES:

1. Measured over operating temperature range

2. Slew rate is measured on rising and falling edges

3

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Electrical Specifications V

= +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = 25°C, unless otherwise specified.

S+

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

V

OS

TCV

I

B

R

IN

C

IN

OS

Input Offset Voltage V

= 2.5V 2 10 mV

CM

Average Offset Voltage Drift (Note 1) 5 µV/°C

Input Bias Current V

= 2.5V 2 50 nA

CM

Input Impedance 1GΩ

Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -0.5 +5.5 V

CMRR Common-Mode Rejection Ratio for V

A

VOL

Open Loop Gain 0.5V ≤ V

from -0.5V to +5.5V 45 66 dB

IN

≤+ 4.5V 75 95 dB

OUT

OUTPUT CHARACTERISTICS

V

V

I

SC

I

OUT

OL

OH

Output Swing Low IL = -5mA 80 150 mV

Output Swing High IL = +5mA 4.85 4.92 V

Short Circuit Current ±120 mA

Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio V

I

S

Supply Current (Per Amplifier) No load 500 750 µA

is moved from 4.5V to 15.5V 60 80 dB

S

DYNAMIC PERFORMANCE

SR Slew Rate (Note 2) 1V ≤ V

t

S

Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

≤ 4V, 20% to 80% 10 V/µs

OUT

BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz

GBWP Gain-Bandwidth Product R

PM Phase Margin R

= 10 kΩ, CL = 10pF 8 MHz

L

= 10 kΩ, CL = 10 pF 50 °

L

CS Channel Separation f = 5MHz (EL5220 & EL5420 only) 75 dB

NOTES:

1. Measured over operating temperature range

2. Slew rate is measured on rising and falling edges

4

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Electrical Specifications V

= +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = 25°C, unless otherwise specified.

S+

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

V

OS

TCV

I

B

R

IN

C

IN

OS

Input Offset Voltage V

= 7.5V 2 14 mV

CM

Average Offset Voltage Drift (Note 1) 5 µV/°C

Input Bias Current V

= 7.5V 2 50 nA

CM

Input Impedance 1GΩ

Input Capacitance 1.35 pF

CMIR Common-Mode Input Range -0.5 +15.5 V

CMRR Common-Mode Rejection Ratio for V

A

VOL

Open Loop Gain 0.5V ≤ V

from -0.5V to +15.5V 53 72 dB

IN

≤ 14.5V 75 95 dB

OUT

OUTPUT CHARACTERISTICS

V

V

I

SC

I

OUT

OL

OH

Output Swing Low IL = -5mA 80 150 mV

Output Swing High IL = +5mA 14.85 14.92 V

Short Circuit Current ±120 mA

Output Current ±30 mA

POWER SUPPLY PERFORMANCE

PSRR Power Supply Rejection Ratio V

I

S

Supply Current (Per Amplifier) No load 500 750 µA

is moved from 4.5V to 15.5V 60 80 dB

S

DYNAMIC PERFORMANCE

SR Slew Rate (Note 2) 1V ≤ V

t

S

Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns

≤ 14V, 20% to 80% 10 V/µs

OUT

BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz

GBWP Gain-Bandwidth Product R

PM Phase Margin R

= 10kΩ, CL = 10pF 8 MHz

L

= 10kΩ, CL = 10 pF 50 °

L

CS Channel Separation f = 5MHz (EL5220 & EL5420 only) 75 dB

NOTES:

1. Measured over operating temperature range

2. Slew rate is measured on rising and falling edges

5

FN7186.4

February 21, 2005

Typical Performance Curves

EL5120, EL5220, EL5420

1800

1600

1400

1200

1000

800

600

400

QUANTITY (AMPLIFIERS)

200

0

VS=±5V

=25°C

T

A

-8-6-4-2-0

-12

-10

INPUT OFFSET VOLTAGE (mV)

TYPICAL
PRODUCTION
DISTRIBUTION

2

4

6

8

10

12

70

VS=±5V

60

50

40

30

20

QUANTITY (AMPLIFIERS)

10

0

1

3

5

7

9

INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)

TYPICAL
PRODUCTION
DISTRIBUTION

11

13

15

17

19

21

FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT

10

VS=±5V

5

0

2.0

0.0

VS=±5V

-5

INPUT OFFSET VOLTAGE (mV)

0 150

50-50 100

TEMPERATURE (°C)

INPUT BIAS CURRENT (nA)

-2.0

0 15050-50 100

TEMPERATURE (°C)

FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE

4.97

4.96

4.95

4.94

OUTPUT HIGH VOLTAGE (V)

4.93

VS=±5V

=5mA

I

OUT

0 150

50-50 100

TEMPERATURE (°C)

OUTPUT LOW VOLTAGE (V)

-4.91

-4.92

-4.93

-4.94

-4.95

-4.96

-4.97

VS=±5V
I

=-5mA

OUT

0 150

50-50 100

TEMPERATURE (°C)

FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE

6

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Typical Performance Curves (Continued)

100

90

80

OPEN LOOP GAIN (dB)

0150

50-50 100

TEMPERATURE (°C)

VS=±5V

=10kΩ

R

L

SLEW RATE (V/µs)

10.40

10.35

10.30

10.25

VS=±5V

0 150

50-50 100

TEMPERATURE (°C)

FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE

VS=±5V

0.55

0.5

700

TA=25°C

600

500

SUPPLY CURRENT (mA)

0.45

0150

50-50 100

TEMPERATURE (°C)

FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs

TEMPERATURE

200

150

100

50

GAIN (dB)

VS=±5V, TA=25°C

0

=10KΩ to GND

R

L

=12pF to GND

C

L

-50
10 10K 100M

100 1K 100K 1M 10M

PHASE

GAIN

FREQUENCY (Hz)

20

-30

-80

-130

-180

-230

400

SUPPLY CURRENT (µA)

300

520

SUPPLY VOLTAGE (V)

100

15

FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs

SUPPLY VOLTAGE

5

0

-5

PHASE (°)

-10
CL=10pF

=1

A

V

=±5V

V

-15

100K

S

1M

FREQUENCY (Hz)

10M

MAGNITUDE (NORMALIZED) (dB)

10kΩ

1kΩ

560Ω

150Ω

100M

FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS R

7

FN7186.4

February 21, 2005

L

EL5120, EL5220, EL5420

Typical Performance Curves (Continued)

20

RL=10kΩ

=1

A

V

V

=±5V

10

S

12pF

50pF

100pF

100M

MAGNITUDE (NORMALIZED) (dB)

-10

-20

-30

0

100K

1000pF

1M

FREQUENCY (Hz)

10M

FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS C

12

)

P-P

10

8

6

VS=±5V
T

=25°C

A

4

=1

A

V

=10kΩ

R

L

2

C

=12pF

L

MAXIMUM OUTPUT SWING (V

Distortion <1%

0

10K 100K

FREQUENCY (Hz)

1M

10M

200

AV=1
V

=±5V

S

160

=25°C

T

A

120

80

40

OUTPUT IMPEDANCE (Ω)

0

10K 100K

FREQUENCY (Hz)

L

FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs

FREQUENCY

80

60

40

CMRR (dB)

20

VS=±5V
T

=25°C

A

0

100

1K

FREQUENCY (Hz)

10K

100K

1M

1M

10M

10M

FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY FIGURE 16. CMRR vs FREQUENCY

80

PSRR+

PSRR-

60

40

PSRR (dB)

20

VS=±5V

=25°C

T

A

0

100

1K

FREQUENCY (Hz)

10K

100K

1M

10M

600

100

10

VOLTAGE NOISE (nV/√Hz)

1

100 100K 100M

FREQUENCY (Hz)

10M1K 10K 1M

FIGURE 17. PSRR vs FREQUENCY FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs

FREQUENCY

8

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Typical Performance Curves (Continued)

0.010

0.009

0.008

0.007

0.006

0.005

THD+ N (%)

0.004
VS=±5V

=10kΩ

R

0.003

L

=1

A

V

0.002
V

=1V

IN

0.001

1K 10K 100K

RMS

FREQUENCY (Hz)

FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs

FREQUENCY

VS=±5V

90

=1

A

V

=10kΩ

R

L

V

=±50mV

IN

70

=25°C

T

A

50

30

OVERSHOOT (%)

10

-60
DUAL MEASURED CHANNEL A TO B

QUAD MEASURED CHANNEL A TO D
OR B TO C

-80

OTHER COMBINATIONS YIELD
IMPROVED REJECTION

-100

X-TALK (dB)

-120

-140
1K

FREQUENCY (Hz)

VS=±5V

=10kΩ

R

L

=1

A

V

=220mV

V

IN

RMS

1M 6M10K 100K

FIGURE 20. CHANNEL SEPARATION vs FREQUENCY

RESPONSE

VS=±5V

4

=1

A

V

=10kΩ

R

3

L

=12pF

C

L

2

T

=25°C

A

1

0

-1

STEP SIZE (V)

-2

-3

-4

0.1%

0.1%

10 100 1K

LOAD CAPACITANCE (pF)

FIGURE 21. SMALL SIGNAL OVERSHOOT vs LOAD

200 400

SETTLING TIME (ns)

FIGURE 22. SETTLING TIME vs STEP SIZE

6000

CAPACITANCE

1V 1µs

VS=±5V

=25°C

T

A

=1

A

V

=10kΩ

R

L

=12pF

C

L

50mV 200ns

VS=±5V

=25°C

T

A

=1

A

V

=10kΩ

R

L

=12pF

C

L

FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE

800

9

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

Pin Descriptions

EL5120 EL5220 EL5420 PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT

1 1 1 VOUTA Amplifier A Output

GND

CIRCUIT 1

4 2 2 VINA- Amplifier A Inverting Input

CIRCUIT 2

3 3 3 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 2)

5 8 4 VS+ Positive Power Supply

5 5 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 2)

6 6 VINB- Amplifier B Inverting Input (Reference Circuit 2)

7 7 VOUTB Amplifier B Output (Reference Circuit 1)

8 VOUTC Amplifier C Output (Reference Circuit 1)

9 VINC- Amplifier C Inverting Input (Reference Circuit 2)

10 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 2)

2 4 11 VS- Negative Power Supply

12 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 2)

13 VIND- Amplifier D Inverting Input (Reference Circuit 2)

14 VOUTD Amplifier D Output (Reference Circuit 1)

V

S+

V

S-

V

S+

V

S-

Applications Information

Product Description

The EL5120, EL5220, and EL5420 voltage feedback
amplifiers are fabricated using a high voltage CMOS
process. They exhibit rail-to-rail input and output capability,
they are unity gain stable, and have low power consumption
(500µA per amplifier). These features make the EL5120,
EL5220, and EL5420 ideal for a wide range of general­purpose applications. Connected in voltage follower mode
and driving a load of 10kΩ and 12pF, the EL5120, EL5220,
and EL5420 have a -3dB bandwidth of 12MHz while
maintaining a 10V/µs slew rate. The EL5120 is a single
amplifier, the EL5220 is a dual amplifier, and the EL5420 is a
quad amplifier.

10

Operating Voltage, Input, and Output

The EL5120, EL5220, and EL5420 are specified with a
single nominal supply voltage from 5V to 15V or a split
supply with its total range from 5V to 15V. Correct operation
is guaranteed for a supply range of 4.5V to 16.5V. Most
EL5120, EL5220, and EL5420 specifications are stable over
both the full supply range and operating temperatures of

-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.

The input common-mode voltage range of the EL5120,
EL5220, and EL5420 extends 500mV beyond the supply
rails. The output swings of the EL5120, EL5220, and
EL5420 typically extend to within 80mV of positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage range even
closer to the supply rails. Figure 25 shows the input and

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

output waveforms for the device in the unity-gain
configuration. Operation is from ±5V supply with a 10kΩ load
connected to GND. The input is a 10V
output voltage is approximately 9.985V

VS=±5V
T

=25°C

A

=1

A

V

V

=10V

IN

P-P

FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND

OUTPUT

sinusoid. The

P-P

.

P-P

OUTPUT INPUT

Short Circuit Current Limit

The EL5120, EL5220, and EL5420 will limit the short circuit
current to ±120mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted
indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never exceeds
±30mA. This limit is set by the design of the internal metal
interconnects.

current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.

The maximum power dissipation allowed in a package is
determined according to:

T

–

P

DMAX

JMAXTAMAX

---------------------------------------------=

Θ

JA

where:

•T

•T

• θ

•P

= Maximum junction temperature

JMAX

= Maximum ambient temperature

AMAX

= Thermal resistance of the package

JA

= Maximum power dissipation in the package

DMAX

The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:

P

DMAX

ΣiVSI

SMAXVS

+( V

OUT

i) I

LOAD

i×–+×[]×=

when sourcing, and:

P

DMAX

ΣiVSI

SMAXVOUT

i( VS-) I

LOAD

i×–+×[]×=

when sinking.

Output Phase Reversal

The EL5120, EL5220, and EL5420 are immune to phase
reversal as long as the input voltage is limited from (V

-0.5V to (V

+) +0.5V. Figure 26 shows a photo of the output

S

-)

S

of the device with the input voltage driven beyond the supply
rails. Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diodes placed in the input stage of the device
begin to conduct and overvoltage damage could occur.

1V 100µs

VS=±2.5V

=25°C

T

A

=1

A

V

=6V

1V

FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT

V

IN

P-P

Power Dissipation

With the high-output drive capability of the EL5120, EL5220,
and EL5420 amplifiers, it is possible to exceed the 125°C
“absolute-maximum junction temperature” under certain load

where:

• i = 1 to 2 for dual and 1 to 4 for quad

•V

= Total supply voltage

S

•I

•V

•I

If we set the two P
can solve for R

= Maximum supply current per amplifier

SMAX

i = Maximum output voltage of the application

OUT

i = Load current

LOAD

equations equal to each other, we

DMAX

i to avoid device overheat. Figures 27

LOAD

and 28 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if P

exceeds the device's power

DMAX

derating curves. To ensure proper operation, it is important
to observe the recommended derating curves in Figures 27
and 28.

11

FN7186.4

February 21, 2005

EL5120, EL5220, EL5420

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD

3

2.500W

2.5

2

1.5

1.136W

1

870mW

0.5

POWER DISSIPATION (W)

θJA=115°C/W

0

0 255075100 150

FIGURE 27. PACKAGE POWER DISSIPATION VS AMBIENT

TEMPERATURE

JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD

1

0.9

833mW

0.8
667mW

0.7

0.6
606mW

0.5
486mW

0.4

0.3

0.2

POWER DISSIPATION (W)

0.1

0

θJA=206°C/W

0 255075100 150

FIGURE 28. PACKAGE POWER DISSIPATION VS AMBIENT

TEMPERATURE

QFN16

θJA=40°C/W

TSSOP14

θJA=100°C/W

1.0W

MSOP8

AMBIENT TEMPERATURE (°C)

SO14

θJA=120°C/W

θJA=150°C/W

MSOP8

AMBIENT TEMPERATURE (°C)

SO14

θJA=88°C/W

QFN16

TSSOP14

θJA=165°C/W

12585

12585

Unused Amplifiers

It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.

Driving Capacitive Loads

The EL5120, EL5220, and EL5420 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the -3dB bandwidth of the device will decrease and the
peaking increase. The amplifiers drive 10pF loads in parallel
with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB
of peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5Ω and 50Ω) can be
placed in series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing peaking
is to add a “snubber” circuit at the output. A snubber is a
shunt load consisting of a resistor in series with a capacitor.
Values of 150Ω and 10nF are typical. The advantage of a
snubber is that it does not draw any DC load current or
reduce the gain

Power Supply Bypassing and Printed Circuit
Board Layout

The EL5120, EL5220, and EL5420 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
connected to ground, a 0.1µF ceramic capacitor should be
placed from V

+ to pin to VS- pin. A 4.7µF tantalum

S

capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.

- pin is

S

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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12

FN7186.4

February 21, 2005