intersil EL5172, EL5372 DATA SHEET

®

EL5172, EL5372

Data Sheet January 25, 2008

250MHz Differential Line Receivers

The EL5172 and EL5372 are single and triple high
bandwidth amplifiers designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signals from twisted-pair
lines or any application where common mode noise injection
is likely to occur.

The EL5172 and EL5372 are stable for a gain of one and
requires two external resistors to set the voltage gain.

The output common mode level is set by the reference pin
(V

), which has a -3dB bandwidth of over 120MHz.

REF

Generally, this pin is grounded but it can be tied to any
voltage reference.

The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload
condition.

The EL5172 is available in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5372 in a 24 Ld QSOP package. Both
are specified for operation over the full -40°C to +85°C
temperature range.

Pinouts

EL5172

(8 LD SOIC, MSOP)

TOP VIEW

EL5372

(24 LD QSOP)

TOP VIEW

FN7311.8

Features

• Differential input range ±2.3V

• 250MHz 3dB bandwidth

• 800V/µs slew rate

• 60mA maximum output current

• Single 5V or dual ±5V supplies

• Low power - 5mA to 6mA per channel

• Pb-free available (RoHS compliant)

Applications

• Twisted-pair receivers

• Differential line receivers

• VGA over twisted-pair

• ADSL/HDSL receivers

• Differential to single-ended amplification

• Reception of analog signals in a noisy environment

FB

IN+

IN-

REF

1

2

+

-

3

4

OUT

8

VS-

7

VS+

6

EN

5

REF1

INP1

INN1

NC

REF2

INP2

INN2

NC

REF3

INP3

INN3

NC

1

2

+

-

3

4

5

6

+

-

7

8

9

10

+

11

-

12

24

23

22

21

20

19

18

17

16

15

14

13

NC

FB1

OUT1

NC

VSP

VSN

NC

FB2

OUT2

EN

FB3

OUT3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002-2005, 2008. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

EL5172, EL5372

Ordering Information

PART NUMBER PART MARKING PACKAGE PKG. DWG. #

EL5172IS 5172IS 8 Ld SOIC (150 mil) MDP0027
EL5172IS-T7* 5172IS 8 Ld SOIC (150 mil) MDP0027
EL5172IS-T13* 5172IS 8 Ld SOIC (150 mil) MDP0027
EL5172ISZ (Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027
EL5172ISZ-T7* (Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027
EL5172ISZ-T13* (Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027
EL5172IY h 8 Ld MSOP (3.0mm) MDP0043
EL5172IY-T7* h 8 Ld MSOP (3.0mm) MDP0043
EL5172IY-T13* h 8 Ld MSOP (3.0mm) MDP0043
EL5172IYZ (Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043
EL5172IYZ-T7* (Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043
EL5172IYZ-T13* (Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) MDP0043
EL5372IU EL5372IU 24 Ld QSOP (150 mil) MDP0040
EL5372IU-T7* EL5372IU 24 Ld QSOP (150 mil) MDP0040
EL5372IU-T13* EL5372IU 24 Ld QSOP (150 mil) MDP0040
EL5372IUZ (Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
EL5372IUZ-T7* (Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
EL5372IUZ-T13* (Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

2

FN7311.8

January 25, 2008

EL5172, EL5372

Absolute Maximum Ratings (T

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

= +25°C) Thermal Information

A

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise

S

Specified.

= TC = T

J

A

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

AC PERFORMANCE

BW -3dB Bandwidth A

=1, CL = 2.7pF 250 MHz

V

A

=2, RF = 1000Ω, CL = 2.7pF 70 MHz

V

AV =10, RF = 1000Ω, CL = 2.7pF 10 MHz
BW ±0.1dB Bandwidth A
SR Slew Rate V

t

STL

t

OVR

Settling Time to 0.1% V
Output Overdrive Recovery Time 20 ns

=1, CL = 2.7pF 25 MHz

V

V

OUT
OUT
OUT

= 3V
= 3V
= 2V

, 20% to 80%, EL5172 550 800 1000 V/µs

P-P

, 20% to 80%, EL5372 550 700 1000 V/µs

P-P
P-P

10 ns

GBWP Gain Bandwidth Product 100 MHz
V

BW (-3dB) V

REF

V

SR V

REF

V

N

I

N

HD2 Second Harmonic Distortion V

HD3 Third Harmonic Distortion V

dG Differential Gain at 3.58MHz R
dθ Differential Phase at 3.58MHz R
e

S

-3dB Bandwidth AV =1, CL = 2.7pF 120 MHz

REF

Slew Rate V

REF

OUT

= 2V

, 20% to 80% 600 V/µs

P-P

Input Voltage Noise at f = 11kHz 26 nV/√Hz
Input Current Noise at f = 11kHz 2 pA/√Hz

= 1V

OUT

V

= 2V

OUT

= 1V

OUT

V

= 2V

OUT

= 150Ω, AV = 2 0.04 %

L

= 150Ω, AV = 2 0.41 °

L

, 5MHz -66 dBc

P-P

, 50MHz -63 dBc

P-P

, 5MHz -84 dBc

P-P

, 50MHz -76 dBc

P-P

Channel Separation at 100kHz EL5372 only 90 dB

INPUT CHARACTERISTICS

V

OS

I

IN

R

IN

C

IN

Input Referred Offset Voltage ±7 ±25 mV
Input Bias Current (VIN, V

INB

, V

)-14-6-3µA

REF

Differential Input Resistance 300 kΩ

Differential Input Capacitance 1pF
DMIR Differential Input Range ±2.1 ±2.38 ±2.5 V
CMIR+ Common Mode Positive Inpu t Range at V
CMIR- Common Mode Positive Input Range at V
V

REFIN+

V

REFIN-

Reference Input Positive Voltage Range VIN+ = VIN- = 0V 3.3 3.7 V

Reference Input Negative Voltage Range VIN+ = VIN- = 0V -3.9 -3.6

+, VIN-3.33.5V

IN

+, VIN- -4.5 -4.3

IN

3

FN7311.8

January 25, 2008

EL5172, EL5372

Electrical Specifications V

+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise

S

Specified. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

CMRR Input Common Mode Rejection Ratio V
Gain Gain Accuracy V

= ±2.5V 75 95 dB

IN

= 1 0.985 1 1.015 V

IN

OUTPUT CHARACTERISTICS

V

OUT

Positive Output Voltage Swing RL = 500Ω to GND 3.3 3.63 V

Negative Output Voltage Swing RL = 500Ω to GND -3.87 -3.5 V
I

(Max) Maximum Output Current RL = 10Ω ±60 ±95 mA

OUT

R

OUT

Output Impedance 100 mΩ

SUPPLY

V

SUPPLY

I

S (on)

I

+ Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5172 80 100 µA

S (off)

I

- Negative Power Supply Current - Disabled -150 -120 -90 µA

S (off)

Supply Operating Range VS+ to VS-4.7511V

Power Supply Current Per Channel - Enabled 4.6 5.6 7 mA

EN

pin tied to 4.8V, EL5372 1.7 5 µA

PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V 50 58 dB

ENABLE

t

EN

t

DS

V

IH

V

IL

I

IH-EN

I

IL-EN

Enable Time 150 ns

Disable Time 1.4 µs

EN Pin Voltage for Power-up VS+ - 1.5 V

EN Pin Voltage for Shut-down VS+ - 0.5 V

EN Pin Input Current High Per Channel At V

EN Pin Input Current Low Per Channel At V

= 5V 40 60 µA

EN

= 0V -10 -3 µA

EN

4

FN7311.8

January 25, 2008

EL5172, EL5372

Pin Descriptions

EL5172 EL5372 PIN NAME PIN FUNCTION

1 FB Feedback input
2 IN+ Non-inverting input
3 IN- Inverting input
4 REF Sets the common mode output voltage level
5EN
6 VS+ Positive supply voltage
7 VS- Negative supply voltage
8 OUT Output voltage

1, 5, 9 REF1, 2, 3 Reference input, controls common-mode output voltage
2, 6, 10 INP1, 2, 3 Non-inverting inputs
3, 7, 11 INN1, 2, 3 Inverting inputs

4, 8, 12, 18, 21, 24 NC No connect; grounded for best crosstalk performance

13, 16, 22 OUT1, 2, 3 Non-inverting outputs
14, 17, 23 FB1, 2, 3 Feedback from outputs

15 EN
19 VSN Negative supply
20 VSP Positive supply

Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5

Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5

5

FN7311.8

January 25, 2008