Intersil Corporation DG445 Datasheet

DG444, DG445

Data Sheet June 1999

Monolithic, Quad SPST, CMOS Analog
Switches

The DG444 and DG445 monolithic CMOS analog switches
are drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
single throw (SPST) analog switches and TTL and CMOS
compatible digital inputs.

These switches feature lower analog ON resistance (<85Ω)
and fasterswitchtime(t

<250ns) compared to the DG211

ON

and DG212. Charge injection has been reduced, simplifying
sample and hold applications.

The improvements in the DG444 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling ±20V signals when operating with ±20V power
supplies.

The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.
The switches in the DG444 and DG445 are identical,
differing only in the polarity of the selection logic.

Pinout

DG444, DG445 (PDIP, SOIC)

TOP VIEW

IN

D
S

GND

S
D

IN

1

1

2

1

3

1

4

V-

5
6

4

7

4

8

4

16

IN

2

15

D

2

14

S

2

13

V+

12

V

L

11

S

3

10

D

3

9

IN

3

File Number

3586.5

Features

• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 85Ω

• Low Power Consumption (P

) . . . . . . . . . . . . . . . . <35µW

D

• Fast Switching Action

-t

(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns

ON

(Max, DG444) . . . . . . . . . . . . . . . . . . . . . . .140ns

-t

OFF

• Low Charge Injection

• Upgrade from DG211/DG212

• TTL, CMOS Compatible

• Single or Split Supply Operation

Applications

• Audio Switching

• Battery Operated Systems

• Data Acquisition

• Hi-Rel Systems

• Sample and Hold Circuits

• Communication Systems

• Automatic Test Equipment

Ordering Information

TEMP.

PART NUMBER

DG444DJ -40 to 85 16 Ld PDIP E16.3
DG444DY -40 to 85 16 Ld SOIC M16.15
DG445DJ -40 to 85 16 Ld PDIP E16.3
DG445DY -40 to 85 16 Ld SOIC M16.15

RANGE (oC) PACKAGE PKG. NO.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

DG444, DG445

Functional Diagrams

DG444

S

1

IN

1

IN

2

IN

3

IN

4

SWITCHES SHOWN FOR LOGIC “1” INPUT

TRUTH TABLE

LOGIC V

IN

0 ≤0.8V ON OFF
1 ≥2.4V OFF ON

IN

1

D

1

S

2

IN

2

D

2

S

3

IN

3

D

3

S

4

IN

4

D

4

DG444 DG445

DG445

Pin Descriptions

PIN SYMBOL DESCRIPTION

S

1

D

1

S

2

D

2

S

3

D

3

S

4

D

4

1IN1Logic Control for Switch 1
2D1Drain (Output) Terminal for Switch 1
3S1Source (Input) Terminal for Switch 1
4 V- Negative Power Supply Terminal
5 GND Ground Terminal (Logic Common)
6S4Source (Input) Terminal for Switch 4
7D4Drain (Output) Terminal for Switch 4
8IN4Logic Control for Switch 4

9IN3Logic Control for Switch 3
10 D
11 S
12 V

Drain (Output) Terminal for Switch 3

3

Source (Input) Terminal for Switch 3

3

Logic Reference Voltage.

L

13 V+ Positive Power Supply Terminal (Substrate)
14 S
15 D
16 IN

Source (Input) Terminal for Switch 2

2

Drain (Output) Terminal for Switch 2

2

Logic Control for Switch 2

2

Schematic Diagram

V+

V

L

IN

X

GND

(One Channel)

S

V-

V+

D

V-

2

DG444, DG445

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) + 0.3V

Digital Inputs, VS, VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,

Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)

Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature (Plastic Packages). . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V

= 5V, VIN = 2.4V, 0.8V (Note 3),

L

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

TEMP

(oC)

(NOTE 4)

MIN

(NOTE 5)

TYP

(NOTE 4)

MAX UNITS

DYNAMIC CHARACTERISTICS

Turn-ON Time, t
Turn-OFF Time, t

ON

OFF

RL = 1kΩ, CL = 35pF, VS = ±10V
(Figure 1)

25 - 120 250 ns

DG444 25 - 110 140 ns

DG445 25 - 160 210 ns
Charge Injection, Q (Figure 2) CL = 1nF, VG = 0V, RG = 0Ω 25--1-pC
OFF Isolation (Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz 25 - 60 - dB
Crosstalk (Channel-to-Channel)

25 - -100 - dB

(Figure 3)
Source OFF Capacitance, C
Drain OFF Capacitance, C
Channel ON Capacitance,

C

+ C

D(ON)

S(ON)

S(OFF)

D(OFF)

f = 1MHz, V

= 0 (Figure 5) 25 - 4 - pF

ANALOG

25 - 4 - pF
25-16-pF

DIGITAL INPUT CHARACTERISTICS

Input Current VIN Low, I

IL

VIN Under Test = 0.8V,

Full -0.5 -0.00001 0.5 µA

All Others = 2.4V

Input Current VIN High, I

IH

VIN Under Test = 2.4V,

Full -0.5 0.00001 0.5 µA

All Others = 0.8V

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Drain-Source ON Resistance,
r

DS(ON)

Source OFF Leakage Current, I

S(OFF)

IS = 10mA, VD = ±8.5V,
V+ = 13.5V, V- = -13.5V

V+ = 16.5V, V- = -16.5V,
VD = ±15.5V, VS = 15.5V

Full -15 - 15 V

25-5085Ω

Full - - 100 Ω

25 -0.5 0.01 0.5 nA
85 -5 - 5 nA

3