intersil DG406, DG407 Data Sheet

®

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DG406, DG407

Data Sheet March 13, 2006

Single 16-Channel/Differential 8-Channel,
CMOS Analog Multiplexers

The DG406 and DG407 monolithic CMOS analog
multiplexers are drop-in replacements for the popular
DG506A and DG507A series devices. They each include an
array of sixteen analog switches, a TTL and CMOS
compatible digital decode circuit for channel selection, a
voltage reference for logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.

These multiplexers feature lower signal ON resistance
(<100Ω) and faster transition time (t

TRANS

< 300ns)
compared to the DG506A and DG507A. Charge injection
has been reduced, simplifying sample and hold applications.

The improvements in the DG406 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30V

signals when operating with ±15V power

P-P

supplies.
The sixteen switches are bilateral, equally matched for AC or

bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.

Pinouts

DG406 (PDIP, SOIC)

V+

1
2

NC

3

NC

4

S

16

S

5

15

S

6

14

S

7

13

S

8

12

S

9

11

S

10

10

S

11

9

GND

12

NC

13
14

A

3

TOP VIEW

D

28

V-

27

S

26

8

S

25

7

S

24

6

S

23

5

S

22

4

S

21

3

20

S

2

S

19

1

EN

18
17

A

0

16

A

1

A

15

2

DG407 (PDIP, SOIC)

TOP VIEW

V+

1
2

D

B

3

NC

4

S

8B

S

5

7B

S

6

6B

S

7

5B

S

8

4B

S

9

3B

S

10

2B

S

11

1B

GND

12
13

NC

14

NC

28

D
V-

27

S

26

S

25

S

24

S

23

S

22

S

21
20

S
S

19

EN

18
17

A

16

A
A

15

FN3116.9

Features

• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω

• Low Power Consumption (P

) . . . . . . . . . . . . . . . <1.2mW

D

• Fast Transition Time (Max). . . . . . . . . . . . . . . . . . . . 300ns

• Low Charge Injection

• TTL, CMOS Compatible

• Single or Split Supply Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Battery Operated Systems

• Data Acquisition

• Medical Instrumentation

• Hi-Rel Systems

• Communication Systems

• Automatic Test Equipment

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

Ordering Information

A

8
7
6
5
4
3
2
1

PART

NUMBER

DG406DJ DG406DJ -40 to 85 28 Ld PDIP E28.6
DG406DJZ

(See Note)
DG406DY DG406DY -40 to 85 28 Ld SOIC M28.3
DG406DY-T DG406DY 28 Ld SOIC Tape and Reel M28.3
DG406DYZ

(See Note)
DG406DYZ-T

(See Note)
DG407DJ DG407DJ -40 to 85 28 Ld PDIP E28.6

0
1
2

DG407DJZ
(Note)

DG407DY DG407DY -40 to 85 28 Ld SOIC M28.3
DG407DYZ

(Note)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are
not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

PART

MARKING

TEMP.

RANGE (°C) PACKAGE

DG406DJZ -40 to 85 28 Ld PDIP*

(Pb-free)

DG406DYZ -40 to 85 28 Ld SOIC

(Pb-free)

DG406DYZ 28 Ld SOIC Tape and Reel

(Pb-free)

DG407DJZ -40 to 85 28 Ld PDIP*

(Pb-free)

DG407DYZ -40 to 85 28 Ld SOIC

(Pb-free)

PKG.

DWG. #

E28.6

M28.3

M28.3

E28.6

M28.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2000, 2003, 2004, 2006. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Schematic Diagram (Typical Channel)

2

FN3116.9

March 13, 2006

DG406, DG407

DG406 TRUTH TABLE

A

A

3

A

2

A

1

EN ON SWITCH

0

XXXX0 None

00001 1
00011 2
00101 3
00111 4
01001 5
01011 6
01101 7
01111 8
10001 9
10011 10
10101 11
10111 12
11001 13
11011 14
11101 15
11111 16

DG407 TRUTH TABLE

A

2

A

1

A

0

EN ON SWITCH PAIR

XXX0 None
0001 1
0011 2
0101 3
0111 4
1001 5
1011 6
1101 7
1111 8

Logic “0” = V
Logic “1” = V

< 0.8V.

AL

> 2.4V.

AH

X = Don’t Care.

3

FN3116.9

March 13, 2006

DG406, DG407

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

Digital Inputs, V

, VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,

S

Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . .100mA

Thermal Resistance (Typical, Note1)

PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(PLCC and SOIC - Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied.

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

NOTES:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. Signals on S

, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.

X

θ

(oC/W)

JA

o

C to 150oC

o

o

C

C

Electrical Specifications T est Conditions: V+ = +15V, V- = -15V, V

PARAMETER TEST CONDITIONS TEMP (

= 0.8V, VAH = 2.4V Unless Otherwise Specified

AL

o

C)

(NOTE 3)

MIN

(NOTE 4)

TYP

(NOTE 3)

MAX UNITS

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

(See Figure 1) 25 - 200 300 ns

Full - - 400 ns

Break-Before-Make Interval, t

OPEN

(See Figure 3) 25 25 50 - ns

Full 10 - - ns

Enable Turn-ON Time, t

ON(EN)

(See Figure 2) 25 - 150 200 ns

Full - - 400 ns

Enable Turn-OFF Time, t

OFF(EN)

25 - 70 150 ns

Full - - 300 ns
Charge Injection, Q C
OFF Isolation, OIRR V

Logic Input Capacitance, C
Source OFF Capacitance, C

IN

S(OFF)

= 1nF, VS = 0V, RS = 0Ω 25 - 40 - pC

L

= 0V, RL = 1kΩ,

EN

f = 100kHz (Note 7)

25 - -69 - dB

f = 1MHz 25 - 7 - pF
VEN = 0V, VS = 0V,

25 - 8 - pF

f = 1MHz

Drain OFF Capacitance, C

D(OFF)

DG406 25 - 160 - pF

VEN = 0V, VD = 0V,
f = 1MHz

DG407 25 - 80 - pF

Drain ON Capacitance, C

D(ON)

DG406 25 - 180 - pF

VEN = 5V, VD = 0V,
f = 1MHz

DG407 25 - 90 - pF

DIGITAL INPUT CHARACTERISTICS

Logic High Input Voltage, V
Logic Low Input Voltage, V
Logic High Input Current, I
Logic Low Input Current, I

AL

INL

AH

INH

VA = 2.4V, 15V Full -1 - 1 µA
VEN = 0V, 2.4V, VA = 0V Full -1 - 1 µA

Full 2.4 - - V

Full - - 0.8 V

ANALOG SWITCH CHARACTERISTICS

Drain-Source ON Resistance,

rDS(ON)

VD = ±10V, IS = +10mA (Note 5) 25 - 50 100 Ω

Full - - 125 Ω

Matching Between Channels,

r

DS(ON)

∆r

DS(ON)

VD = 10V, -10V (Note 6) 25 - 5 - %

4

FN3116.9

March 13, 2006