intersil DG406, DG407 Data Sheet

®

A A A A

A

DG406, DG407

Data Sheet March 13, 2006

Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers

The DG406 and DG407 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A and DG507A series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present.

These multiplexers feature lower signal ON resistance (<100Ω) and faster transition time (t

TRANS

< 300ns) compared to the DG506A and DG507A. Charge injection has been reduced, simplifying sample and hold applications.

The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30V

signals when operating with ±15V power

P-P

supplies. The sixteen switches are bilateral, equally matched for AC or

bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range.

Pinouts

DG406 (PDIP, SOIC)

V+

1 2

NC

3

NC

4

S

16

S

5

15

S

6

14

S

7

13

S

8

12

S

9

11

S

10

S

11

9

GND

12

NC

13 14

A

3

TOP VIEW

D

28

V-

27

S

26

8

S

25

7

S

24

6

S

23

5

S

22

4

S

21

3

20

S

2

S

19

1

EN

18 17

A

0

16

A

1

A

15

2

DG407 (PDIP, SOIC)

TOP VIEW

V+

1 2

D

B

3

NC

4

S

8B

S

5

7B

S

6

6B

S

7

5B

S

8

4B

S

9

3B

S

10

2B

S

11

1B

GND

12 13

NC

14

NC

28

D V-

27

S

26

S

25

S

24

S

23

S

22

S

21 20

S S

19

EN

18 17

A

16

A A

15

FN3116.9

Features

• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω

• Low Power Consumption (P

) . . . . . . . . . . . . . . . <1.2mW

D

• Fast Transition Time (Max). . . . . . . . . . . . . . . . . . . . 300ns

• Low Charge Injection

• TTL, CMOS Compatible

• Single or Split Supply Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Battery Operated Systems

• Data Acquisition

• Medical Instrumentation

• Hi-Rel Systems

• Communication Systems

• Automatic Test Equipment

Related Literature

• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”

Ordering Information

A

8 7 6 5 4 3 2 1

PART

NUMBER

DG406DJ DG406DJ -40 to 85 28 Ld PDIP E28.6 DG406DJZ

(See Note) DG406DY DG406DY -40 to 85 28 Ld SOIC M28.3 DG406DY-T DG406DY 28 Ld SOIC Tape and Reel M28.3 DG406DYZ

(See Note) DG406DYZ-T

(See Note) DG407DJ DG407DJ -40 to 85 28 Ld PDIP E28.6

0 1 2

DG407DJZ (Note)

DG407DY DG407DY -40 to 85 28 Ld SOIC M28.3 DG407DYZ

(Note)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

TEMP.

RANGE (°C) PACKAGE

DG406DJZ -40 to 85 28 Ld PDIP*

(Pb-free)

DG406DYZ -40 to 85 28 Ld SOIC

(Pb-free)

DG406DYZ 28 Ld SOIC Tape and Reel

(Pb-free)

DG407DJZ -40 to 85 28 Ld PDIP*

(Pb-free)

DG407DYZ -40 to 85 28 Ld SOIC

(Pb-free)

PKG.

DWG. #

E28.6

M28.3

E28.6

M28.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Schematic Diagram (Typical Channel)

2

FN3116.9

March 13, 2006

DG406, DG407

DG406 TRUTH TABLE

A

3

A

2

A

1

EN ON SWITCH

0

XXXX0 None

00001 1 00011 2 00101 3 00111 4 01001 5 01011 6 01101 7 01111 8 10001 9 10011 10 10101 11 10111 12 11001 13 11011 14 11101 15 11111 16

DG407 TRUTH TABLE

A

2

A

1

A

0

EN ON SWITCH PAIR

XXX0 None 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8

Logic “0” = V Logic “1” = V

< 0.8V.

AL

> 2.4V.

AH

X = Don’t Care.

3

FN3116.9

March 13, 2006

DG406, DG407

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

Digital Inputs, V

, VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,

S

Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . .100mA

Thermal Resistance (Typical, Note1)

PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(PLCC and SOIC - Lead Tips Only)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied.

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTES:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. Signals on S

, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.

X

θ

(oC/W)

JA

o

C to 150oC

o

C

Electrical Specifications T est Conditions: V+ = +15V, V- = -15V, V

PARAMETER TEST CONDITIONS TEMP (

= 0.8V, VAH = 2.4V Unless Otherwise Specified

AL

o

C)

(NOTE 3)

MIN

(NOTE 4)

TYP

(NOTE 3)

MAX UNITS

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

(See Figure 1) 25 - 200 300 ns

Full - - 400 ns

Break-Before-Make Interval, t

OPEN

(See Figure 3) 25 25 50 - ns

Full 10 - - ns

Enable Turn-ON Time, t

ON(EN)

(See Figure 2) 25 - 150 200 ns

Full - - 400 ns

Enable Turn-OFF Time, t

OFF(EN)

25 - 70 150 ns

Full - - 300 ns Charge Injection, Q C OFF Isolation, OIRR V

Logic Input Capacitance, C Source OFF Capacitance, C

IN

S(OFF)

= 1nF, VS = 0V, RS = 0Ω 25 - 40 - pC

L

= 0V, RL = 1kΩ,

EN

f = 100kHz (Note 7)

25 - -69 - dB

f = 1MHz 25 - 7 - pF VEN = 0V, VS = 0V,

25 - 8 - pF

f = 1MHz

Drain OFF Capacitance, C

D(OFF)

DG406 25 - 160 - pF

VEN = 0V, VD = 0V, f = 1MHz

DG407 25 - 80 - pF

Drain ON Capacitance, C

D(ON)

DG406 25 - 180 - pF

VEN = 5V, VD = 0V, f = 1MHz

DG407 25 - 90 - pF

DIGITAL INPUT CHARACTERISTICS

Logic High Input Voltage, V Logic Low Input Voltage, V Logic High Input Current, I Logic Low Input Current, I

AL

INL

AH

INH

VA = 2.4V, 15V Full -1 - 1 µA VEN = 0V, 2.4V, VA = 0V Full -1 - 1 µA

Full 2.4 - - V

Full - - 0.8 V

ANALOG SWITCH CHARACTERISTICS

Drain-Source ON Resistance,

rDS(ON)

VD = ±10V, IS = +10mA (Note 5) 25 - 50 100 Ω

Full - - 125 Ω

Matching Between Channels,

r

DS(ON)

∆r

DS(ON)

VD = 10V, -10V (Note 6) 25 - 5 - %

4

FN3116.9

March 13, 2006

DG406, DG407

Electrical Specifications T est Conditions: V+ = +15V, V- = -15V, V

PARAMETER TEST CONDITIONS TEMP (

Source OFF Leakage Current, I

Drain OFF Leakage Current, I

S(OFF)

D(OFF)

VEN = 0V, VS = ±10V, V

= +10V

D

= 0.8V, VAH = 2.4V Unless Otherwise Specified (Continued)

AL

o

C)

(NOTE 3)

MIN

(NOTE 4)

TYP

(NOTE 3)

MAX UNITS

25 -0.5 0.01 0.5 nA

Full -5 - 5 nA

DG406 25 -1 0.04 1 nA

Full -40 - 40 nA

DG407 25 -1 0.04 1 nA

Full -20 - 20 nA Drain ON Leakage Current, I

D(ON)

VS = VD = ±10V (Note 5)

DG406 25 -1 0.04 1 nA

Full -40 - 40 nA

DG407 25 -1 0.04 1 nA

Full -20 - 20 nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V

= VA = 0V or 5V

EN

(Standby)

25 - 13 30 µA

Full - - 75 µA Negative Supply Current, I- 25 -1 -0.01 - µA

Full -10 - - µA Positive Supply Current, I+ V

= 2.4V, VA = 0V

EN

(Enabled)

25 - 80 100 µA

Full - - 200 µA Negative Supply Current, I- 25 -1 -0.01 - µA

Full -10 - - µA

Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, V

Unless Otherwise Specified

PARAMETER

DYNAMIC CHARACTERISTICS

Switching Time of Multiplexer, t

Enable Turn-ON Time, t

TRANS

ON(EN)

Enable Turn-OFF Time, t

OFF(EN)

Charge Injection, Q C

TEST

CONDITIONS TEMP (

VS1 = 8V, VS8 = 0V, V

= 2.4V

IN

V

= 2.4V, V

INH

V

= 5V

S1

= 1nF, VS = 6V,

L

R

= 0Ω

S

INL

= 0V,

o

C)

25 - 300 450 ns

25 - 250 600 ns 25 - 150 300 ns

25 - 20 - pC

= 0.8V, VAH = 2.4V,

AL

(NOTE 3)

MIN

(NOTE 4)

TYP

(NOTE 3)

MAX UNITS

5

FN3116.9

March 13, 2006

DG406, DG407

Electrical Specifications Single Supply Test Conditions: V+ = 12V, V- = 0V, V

= 0.8V, VAH = 2.4V,

AL

Unless Otherwise Specified (Continued)

PARAMETER

TEST

CONDITIONS TEMP (

o

C)

(NOTE 3)

MIN

(NOTE 4)

TYP

(NOTE 3)

MAX UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Drain-Source ON-Resistance, r

DS(ON)

r Channels (Note 6), ∆r

Matching Between

DS(ON)

Source Off Leakage Current, I Drain Off Leakage Current, I

S(OFF)

D(OFF)

VD = 3V, 10V, IS = -1mA (Note 5)

VEN = 0V, VD = 10V or 0.5V, V

= 0.5V or 10V

S

Full 0 - 12 V

25 - 90 120 Ω

25 - 5 - %

25 - 0.01 - nA

DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA

Drain On Leakage Current, I

D(ON)

VS = VD = ±10V (Note 5)

DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current (I+) (Standby)

Negative Supply Current (I-) (Enabled)

= 0V or 5V,

V

EN

V

= 0V or 5V

A

25 - 13 30 µA

Full - 13 75 µA

25 -1 -0.01 - µA

Full -5 -0.01 - µA

NOTES:

3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

4. Typical values are for Design Aid Only, not guaranteed nor production tested.

5. Sequence each switch ON.

6. ∆r

DS(ON)

= (r

DS(ON)

(Max) - r

DS(ON)

(Min)) ÷ r

DS(ON)

average.

7. Worst case isolation occurs on channel 8B due to proximity to the drain pin.

Test Circuits and Waveforms

+15V

V+

S2 - S

V-

-15V

6

S

1

15

S

16

D

LOGIC

INPUT

+2.4V

EN A3

A A

A

2 1

0

DG406

GND

FIGURE 1A. DG406 TEST CIRCUIT FIGURE 1B. DG407 TEST CIRCUIT

±10V

±

10V

+15V

V+

DG407

-15V

S

V-

+2.4V

LOGIC INPUT

V

O

35pF300Ω50Ω

EN

A

2

A

1

A

0

GND

† = S1A - S8A, S2B - S7B, D

±10V

1B

†

±

8B

D

10V

B

A

V

O

35pF300Ω50Ω

FN3116.9

March 13, 2006

Test Circuits and Waveforms (Continued)

INPUT

V

3V 0V

S

V

S1B

0V

O

V

S8B

t

TRANS

FIGURE 1C. MEASUREMENT POINTS

FIGURE 1. TRANSITION TIME

LOGIC

SWITCH

OUTPUT

DG406, DG407

50%

ON

1

80%

S8 ON

50%

V

t

< 20ns

r

< 20ns

t

f

V

80%

S1

S8

t

TRANS

LOGIC INPUT V

A A A

EN

2 1 0

DG407

D

GND

+15V

V+

AND D

A

1B

-5V

S

†

B

V-

+15V

V+

A3 A

2

S2 - S

A

1

DG406

A

IN

EN

0

GND

V-

-5V

S

1

16

D

V

O

LOGIC INPUT V

IN

35pF300Ω50Ω

-15V † = S1A - S8A, S2B - S8B, D

-15V

A

FIGURE 2A. DG406 TEST CIRCUIT FIGURE 2B. DG407 TEST CIRCUIT

tr < 20ns

< 20ns

t

LOGIC

INPUT

V

3V

0V

50%

IN

t

ON(EN)

50%

0V

f

t

OFF(EN)

SWITCH OUTPUT

V

O

V

90%

V

O

FIGURE 2C. MEASUREMENT POINTS

FIGURE 2. ENABLE SWITCHING TIMES

V

O

35pF300Ω50Ω

LOGIC

INPUT

+15V

3V

LOGIC

+2.4V

EN A3

A A

A

2 1

0

DG406 DG407

GND

V+

AND D

-15V

ALL S

D

V-

+5V (VS)

A

D,

B

V

O

35pF300Ω50Ω

INPUT

SWITCH

OUTPUT

V

0V

V

S

O

0V

t

OPEN

FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS

FIGURE 3. BREAK-BEFORE-MAKE INTERVAL

7

80%

tr < 20ns

< 20ns

t

f

March 13, 2006

FN3116.9

Typical Performance Curves

DG406, DG407

160

140

120

100

±5V

80

±8V

±15V

±12V

±10V

, DRAIN VOLTAGE (V)

V

D

vs VD AND SUPPLY FIGURE 5. r

DS(ON)

V+ = 7.5V

V- = 0V

60

, ON RESISTANCE (Ω)

40

DS(ON)

r

±20V

20

0

-20 -16 -12 -8 -4 0 4 8 12 16 20

FIGURE 4. r

240

200

160

10V

120

12V

, ON-RESISTANCE (Ω)

80

DS(ON)

r

40

15V

20V

22V

80

70

125oC

60

85oC

50

25oC

40

0oC

30

, ON-RESISTANCE (Ω)

20

DS(ON)

r

10

0

-15 -10 -5 5 10015 V

, DRAIN VOLTAGE (V)

D

vs VD AND TEMPERATURE

DS(ON)

120

V+ = 15V, V- = -15V V

= -VD FOR I

S

80

VD = V

S(OPEN)

D(OFF)

FOR I

D(ON)

-40oC

-55oC V+ = 15V

V- = -15 V

40

I

0

, CURRENT (pA)

S

-40

, I

D

I

S(OFF)

DG407 I

D(ON)

DG406 I

, I

D(OFF)

D(ON)

, I

D(OFF)

-80

0

048121620

, DRAIN VOLTAGE (V)

V

D

100nA

10nA

FIGURE 6. r

V+ = 15V, V- = -15V

OR VD = ±10V

V

S

vs VD AND SUPPLY FIGURE 7. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE

DS(ON)

1nA

I

, I

D(ON)

100pA

, CURRENT (A)

S

, I

D

I

10pA

D(OFF)

I

S(OFF)

1pA

0.1pA

-55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (

FIGURE 8. I

, IS LEAKAGE vs TEMPERATURE FIGURE 9. SWITCHING TIMES vs BIPOLAR SUPPLIES

D

o

C)

-120

-15

-10 -5 5 10015 V

, VD, SOURCE DRAIN VOLTAGE (V)

S

350

300

250

t

TRANS

200

t

150

TIME (ns)

ON(EN)

100

t

50

0

5101520

OFF(EN)

V

, SUPPLY VOLTAGE (±V)

SUPPLY

8

FN3116.9

March 13, 2006

Typical Performance Curves (Continued)

DG406, DG407

ISOL (dB)

-140

-120

-100

-80

-60

-40

-20

0 100

1K 10K 1M100K 10M

f, FREQUENCY (Hz)

700

600

500

t

400

300

TIME (ns)

200

100

0

5101520

TRANS

t

ON(EN)

t

OFF(EN)

V+, SUPPLY VOLTAGE (V)

V- = 0V

FIGURE 10. SWITCHING TIMES vs SINGLE SUPPLY FIGURE 11. OFF ISOLATION vs FREQUENCY

10

EN = 5V, AX = 0V OR 5V

8 6 4 2 0

-2

I, CURRENT (mA)

-4

-6

-8

-10 10

100 1K 100K 1M10K 10M

f, FREQUENCY (Hz)

I+

I

GND

I-

300

V+ = 15V, V- = -15V

280 260 240 220 200 180 160

TIME (ns)

140 120 100

80 60

-55 -35 -15 5 25 45 65 85 105 125

t

TRANS

t

ON(EN)

t

OFF(EN)

TEMPERATURE (

o

C)

FIGURE 12. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 13. t

3

2

,(V)

A

V

1

0

5101520

V

, SUPPLY VOLTAGE (±V)

SUPPLY

FIGURE 14. SWITCHING THRESHOLD vs SUPPLY VOLTAGE

9

ON/tOFF

vs TEMPERATURE

FN3116.9

March 13, 2006

Die Characteristics

DG406, DG407

DIE DIMENSIONS:

2490µm x 4560µm x 485µm

METALLIZATION:

Type: SiAl Thickness: 12k

Å ±1kÅ

Metallization Mask Layout

S

16

S

15

S

14

S

13

DG406

PASSIVATION:

Type: Nitride Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

4

2

9.1 x 10

DNC V+

A/cm

V-

S

5

S

7

S

6

S

5

S

12

S

11

S

10

S

9

GND

A

3

A

1A2

A

EN

0

4

S

3

S

2

S

1

10

FN3116.9

March 13, 2006

Die Characteristics

DG406, DG407

DIE DIMENSIONS:

2490µm x 4560µm x 485µm

METALLIZATION:

Type: SiAl Thickness: 12k

Å ±1kÅ

Metallization Mask Layout

S

8B

S

7B

S

6B

PASSIVATION:

Type: Nitride Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

4

2

9.1 x 10

DG407

D

B

V+

A

A/cm

V-D

S

8A

S

7A

S

6A

S

5A

S

5B

S

4B

S

3B

S

2B

S

1B

A

NCGND

1A2

ENA

0

S

4A

S

3A

S

2A

S

1A

11

FN3116.9

March 13, 2006

DG406, DG407

Dual-In-Line Plastic Packages (PDIP)

N

-C-

E1

-B-

E

C

L

e

A

e

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

12 3 N/2

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

e

A

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

B

e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

12

FN3116.9

March 13, 2006

Small Outline Plastic Packages (SOIC)

DG406, DG407

N

INDEX AREA

123

SEA TING PLANE

-AD

e

B

0.25(0.010) C AM BS

M

E

-B-

A

-C-

0.25(0.010) BM M

H

α

µ

A1

0.10(0.004)

L

h x 45

o

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

C

h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6

N28 287

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

13

FN3116.9

March 13, 2006

intersil DG406, DG407 Data Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual