DG401, DG403, DG405
Data Sheet June 1999
Monolithic CMOS Analog Switches
The DG401, DG403 and DG405 monolithic CMOS analog
switches have TTL and CMOS compatible digital inputs.
These switches feature low analog ON resistance (<45Ω)
and fast switch time (t
< 150ns). Low charge injection
ON
simplifies sample and hold applications.
The improvements in the DG401/403/405 series are made
possible by using a high voltage silicon-gate process . An
epitaxial layer pre vents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30V
signals. Po w er supplies may be
P-P
single-ended from +5V to +34V, or split from ±5V to ±17V.
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The three
differentdevicesprovidetheequivalentoftwoSPST(DG401),
two SPDT (DG403) or two DPST (DG405) relay s witch
contacts with CMOS or TTL level activ ation. The pinout is
similar, permitting a standard layout to be used, choosing the
switch function as needed.
Pinouts
DG401 (PDIP, SOIC)
TOP VIEW
16
D
NC
NC
NC
NC
NC
NC
D
1
1
2
3
4
5
6
7
8
2
S
1
15
IN
1
14
V-
13
GND
V
12
L
11
V+
IN
10
2
9
S
2
File Number
3284.6
Features
• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 45Ω
• Low Power Consumption (P
) . . . . . . . . . . . . . . . . . . <35µW
D
• Fast Switching Action
-t
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100ns
-t
OFF
• Low Charge Injection
• DG401 Dual SPST; Same Pinout as HI-5041
• DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
• DG405 Dual DPST; DG184, HI-5045, IH5145
• TTL, CMOS Compatible
• Single or Split Supply Operation
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Ordering Information
TEMP. RANGE
PART NUMBER
DG401DJ -40 to 85 16 Ld PDIP E16.3
DG401DY -40 to 85 16 Ld SOIC M16.15
DG403DJ -40 to 85 16 Ld PDIP E16.3
(oC) PACKAGE PKG. NO.
DG403, DG405 (SOIC)
TOP VIEW
16
D
NC
D
D
NC
D
1
1
2
3
3
4
S
3
5
S
4
6
4
7
8
2
S
1
15
IN
14
V-
13
GND
12
V
L
11
V+
10
IN
9
S
2
NOTE: (NC) No Connection.
1
DG403DY -40 to 85 16 Ld SOIC M16.15
DG405DY -40 to 85 16 Ld SOIC M16.15
1
TRUTH TABLE
DG401 DG403 DG405
LOGIC
SWITCH SWITCH 1, 2 SWITCH 3, 4 SWITCH
0 OFF OFF ON OFF
2
1 ON ON OFF ON
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
DG401, DG403, DG405
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V
Digital Inputs VS, VD (Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max). . 100mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
= 2.4V, 0.8V (Note 3), VL= 5V,
IN
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TEMP
(
(NOTE 4)
o
C)
MIN
(NOTE5)
TYP
(NOTE4)
MAX UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Turn-OFF Time, t
ON
OFF
Break-Before-Make Time Delay (DG403), t
RL = 300Ω, CL = 35pF 25 - 100 150 ns
25 - 60 100 ns
RL = 300Ω, CL = 35pF 25 5 12 - ns
D
Charge Injection, Q (Figure 3) CL = 10nF, VG = 0V, RG = 0Ω 25 - 60 - pC
OFF Isolation (Figure 4) RL = 100Ω, CL = 5pF, f = 1MHz 25 - 72 - dB
Crosstalk (Channel-to-Channel) (Figure 6) 25 - -90 - dB
Source OFF Capacitance, C
Drain OFF Capacitance, C
Channel ON Capacitance, C
S(OFF)
D(OFF)
D(ON)
+ C
S(ON)
f = 1MHz, VS = VD = 0V (Figure 7) 25 - 12 - pF
25 - 12 - pF
25 - 39 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current with VIN Low, I
Input Current with VIN High, I
IL
IH
VINUnder Test = 0.8V, All Others = 2.4V Full -1 0.005 1 µA
VINUnder Test = 2.4V, All Others = 0.8V Full -1 0.005 1 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Drain-Source ON Resistance, r
r
Matching Between Channels, ∆r
DS(ON)
Source OFF Leakage Current, I
Drain OFF Leakage Current, I
DS(ON)
S(OFF)
D(OFF)
DS(ON)
V+ = 13.5V, V- = -13.5V,
IS = 10mA, VD = ±10V
V+ = 16.5V, V- = -16.5V,
IS = -10mA, VD = 5, 0, -5V
V+ = 16.5V, V- = -16.5
VD = ±15.5V, VS = 15.5V
Full -15 - 15 V
25 - 20 45 Ω
Full - - 55 Ω
25 - 3 3 Ω
Full - - 5 Ω
25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
25 -0.5 -0.01 0.5 nA
Full -5 - 5 nA
Channel ON Leakage Current, I
D(ON)+IS(ON)
V± = ±16.5V, VD = VS = ±15.5V 25 -1 -0.04 1 nA
Full -10 - 10 nA
3