Intersil Corporation DECIMATE Datasheet

DECIMATE™

Data Sheet May 1999

IntersilHSP43220 Decimating Digital Filter Development Software

Intersil DECIMATE Development Software assiststhedesign engineer to prototype designs for the Intersil HSP43220 Decimating Digital ﬁlter (DDF). Developed speciﬁcallyfor the DDF, this software consists of three integrated modules: DDF Design, DDF Simulator and DDF PROM. The Design module designs a ﬁlter from a set of user speciﬁcations for the DDF. The Simulator module models the DDF’s internal operation. The PROM module uses the device conﬁguration created by the Design module to build a PROM data ﬁle that can be used to store and download the DDF conﬁguration.

DDF System Design

The DDF consists of two stages: a High Decimation Filter (HDF) and a Finite Impulse Response (FIR) filter. Together these providea unique narrowband, lowpass filter.Because of this unique architecture, special software is required to configure the device for a giv en set of filter parameters . This software uses system level filter par ameters (listed below) to perform the trade off analysis and calculate the values for the DDF’s Configuration Registers and FIR coefficients.

Design speciﬁcations are supplied by the user in terms of:

1. Input sample frequency.

2. Required output sample frequency.

3. Passband signal bandwidth.

4. Transition bandwidth.

5. Amount of attenuation allowed in the passband.

6. Amount of stopband attenuation required for signals outside of the band of interest.

This information is entered into a menu screen (See Figure

1), providing immediate feedback on the design validity.The design module calculates the order of the HDF, HDF decimation required, the FIR input data rate, minimum clock frequency for the FIR, FIR order and decimation required in the FIR.

The design module will then generate the FIR ﬁlter. Four different methods are provided for the FIR design:

1. A Standard FIR automatically designed by the module using the Parks-McClellan method to compute the coefﬁcients of an equiripple (Chebyshev) ﬁlter.

2. Any FIR imported into the Design module from another FIR design program.

3. A precompensated FIR which is automatically designed by the module to compensate for the roll-off in the passband of the HDF frequency response.

4. The FIR may alsobe bypassedin which case the optimal HDF is designed from the user speciﬁcations.

File Number

Frequency response curves are then displayed showing the resulting responses in the HDF, FIR and for the entire chip using the givenﬁlter design. Figure 2 is a typical display.The user may save this frequency response data for further analysis. The design module also creates a report ﬁle documenting the ﬁlter design and providing the coefﬁcients and setup register values for programming the device.

3368.1

DDF Simulator

The simulator provides an accurate simulation of the device before any hardware is built. It can be used to simulate any ﬁlter designed with DECIMATE. The simulator takes into account the ﬁxed point bus widths and pipeline delays for every element in the DDF.

The simulator provides the user with an input signal which can be usedto stimulate the ﬁlter.This signal is created from the options shown in Table 1. The user can select a pure step, impulse, cosine, chirp, uniform or Gaussian noise as the input signal, or a morecomplex signal can be generated by combining that data with an option selected from the Signal #2 column, with the combining operator chosen from the middle column. The user can also import a signal from an outside source.

TABLE 1.

SIGNAL #1 OPERATION SIGNAL #2

Step Step Impulse No Operation Impulse COSlNE Add COSINE Chirp Concatenate Chirp Uniform Noise Multiply Uniform Noise Gaussian Noise Gaussian Noise

Imported From Outside

Probes are provided to select specific areas to graphically display data values, as w ell as sa v e into data files f or further processing. The DDF Simulator has two lev els; the DDF Simulator Specification Screen and the DDF Simulator Main Screen.

The Speciﬁcation Screen (see Figure 3) is used to input the simulation parameters. The user selects display modes in either continuous or decimated format and data formats in either decimal or hexadecimal. The Speciﬁcation Screen also provides for selection of the input signal.

The simulator main screen (see Figure 4) deﬁnes the simulator test probes and displays the data values per clock cycle. The interactive simulator screen consists of the HSP43220 Block Diagram, test probes and register

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

DECIMATE™ is a trademark of Intersil Corporation.

DECIMATE

contents. The user selects the step size of the input sample clock and also selects the probes to be monitored. The simulator will then clock through the speciﬁed number of clock cycles and display the resulting timedomain response. Figure 5 shows a typical probe display.

Monarch 2.0 DSP Design Software

DECIMATE is fully integrated with Monarch 2.0 professional DSP design software. Monarch is a full featured DSP package with FIR lIR ﬁlter design and analysis, two dimensional and three dimensional viewing, a programmable signal/systems laboratory with 100 + DSP/Math functions, extensive ﬁxed-point support and

DESIGN MODULE SIMULATOR MODULE PROM MODULE

HSP43220 DDF FILTER SPECIFICATION

Filter File Input Sample Rate

D E C I M

Output Rate Passband Transition Band Passband Atten Stopband Atten

FIR Type STANDARD

A T E

HDF Order HDF Decimation HDF Scale Factor

: : : : : : :

: : :

PRES.DDF

330

0.6903

FFTs/IFETs Monarch is available separately from The Athena Group, Inc.

When used with Monarch 2.0, DECIMATE becomes a full feature design environment for a DSP system. Data can easily be transferred from DECIMATE modules to the Monarch modules for further analysis.

System Requirements

IBM PC™, XT™, AT™, PS/2 computer or 100% compatible with 640K RAM running MS/PC-DOS 2.0 or higher One MegaByte of ﬁxed-disk space with 5.25” or3.5” ﬂoppy drive. CGA, MCGA, EGA, VGA, 8514, or Hercules Graphics Adapter. A Math coprocessor is strongly recommended.

100 700

MHz kHz kHz

Hz dB

Design Mode Generate Report Display Response Save Freq Responses Save FIR Response

FIR Input Rate FIR Clock (min) FIR Order FIR Decimation

: : : :

100 509

: : : : :

AUTO YES LOG YES YES

kHz MHz

FIGURE 1. FILTER SPECIFICATION MENU

IBM PC, XT, AT, PS/2™ are trademarks of IBM Corporation.

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