1
June 1998
82C55A
CMOS Programmable
Peripheral Interface
Features
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Description
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Ordering Information
P AR T NUMBERS
P ACKAGE
TEMPERA TURE
RANGE
PKG.
NO.5MHz 8MHz
CP82C55A-5 CP82C55A
40 Ld PDIP
0oC to 70oC E40.6
IP82C55A-5 IP82C55A -40
o
C to 85oC E40.6
CS82C55A-5 CS82C55A
44 Ld PLCC
0
o
C to 70oC N44.65
IS82C55A-5 IS82C55A -40
o
C to 85oC N44.65
CD82C55A-5 CD82C55A
40 Ld
CERDIP
0
o
C to 70oC F40.6
ID82C55A-5 ID82C55A -40
o
C to 85oC F40.6
MD82C55A-5/B MD82C55A/B -55
o
C to 125oC F40.6
8406601QA 8406602QA SMD# F40.6
MR82C55A-5/B MR82C55A/B
44 Pad
CLCC
-55
o
C to 125oC J44.A
8406601XA 8406602XA SMD# J44.A
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
TOP VIEW
82C55A (PLCC)
TOP VIEW
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PA4
PA5
PA6
PA7
WR
RESE
T
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
PB6
PB5
PB4
PB3
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
4065 321444342414
9
10
11
8
7
12
13
17
16
15
14
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
GND
NC
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
V
CC
NC
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
NC
CS
RD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
RD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
NC
PC2
NC
44 4342 41 40
39
38
37
36
35
34
33
32
31
30
29
2827
123456
262524232221201918
7
8
9
10
11
12
13
14
15
16
17
File Number 2969.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
2
Functional Diagram
Pin Description
SYMBOL
PIN
NUMBER TYPE DESCRIPTION
V
CC
26 VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
recommended for decoupling.
GND 7 GROUND
D0-D7 27-34 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CS 6 I CHIP SELECT: Chip select isan active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
RD 5 I READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA BUS
BUFFER
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BI-DIRECTIONAL
DATA BUS
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
8-BIT
INTERNAL
DATA BUS
82C55A
3
Functional Description
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a control word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
82C55A BASIC OPERATION
A1 A0 RD WR CS
INPUT OPERATION
(READ)
00010Port A → Data Bus
01010Port B → Data Bus
10010Port C → Data Bus
11010Control Word → Data Bus
OUTPUT OPERATION
(WRITE)
00100Data Bus → Port A
01100Data Bus → Port B
10100Data Bus → Port C
11100Data Bus → Control
DISABLE FUNCTION
XXXX1Data Bus → Three-State
X X 1 1 0 Data Bus → Three-State
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DAT A
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BI-DIRECTIONAL
DATA BUS
I/O
PA7-
I/O
PC7-
I/O
PC3-
I/O
PB7-
BUFFER
BUS
PB0
PC0
PC4
PA0
8-BIT
INTERNAL
DATA BUS
82C55A
4
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or “personality” to further enhance the power and flexibility of
the 82C55A.
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
Operational Description
Mode Selection
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pullup or pulldown resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
MASTER
RESET
OR MODE
CHANGE
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
EXTERNAL
PORT A PIN
OUTPUT MODE
INPUT MODE
RESET
OR MODE
CHANGE
INTERNAL
DATA IN
INTERNAL
DATA OUT
(LATCHED)
EXTERNAL
PORT B, C
OUTPUT MODE
PIN
P
V
CC
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
DATA BUS
8 I/O
B
PB7-PB0
4 I/O
PC3-PC0
4 I/O
C
PC7-PC4
8 I/O
A
PA7-PA0
CONTROL BUS
ADDRESS BUS
RD, WR
82C55A
D7-D0 A0-A1
CS
MODE 0
8 I/O
B
PB7-PB0 CONTROL
C
8 I/O
A
PA7-PA0
MODE 1
OR I/O
CONTROL
OR I/O
8 I/O
B
PB7-PB0
C
BI-
A
PA7-PA0
MODE 2
CONTROL
DIRECTIONAL
FIGURE 4. MODE DEFINITION FORMAT
D7 D6 D5 D4 D3 D2 D1 D0
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
GROUP B
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
GROUP A
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
CONTROL WORD
82C55A
5
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
Interrupt Control Functions
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply written to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Input are not latched
• 16 different Input/Output configurations possible
FIGURE 5. BIT SET/RESET FORMAT
D7 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0
BIT SET/RESET FLAG
CONTROL WORD
DON’T
CARE
XXX
0 = ACTIVE
1234567
01010101
00110011
00001111
B0
B1
B2
MODE 0 PORT DEFINITION
A B GROUP A
#
GROUP B
D4 D3 D1 D0 PORTA
PORTC
(Upper) PORTB
PORTC
(Lower)
0 0 0 0 Output Output 0 Output Output
0 0 0 1 Output Output 1 Output Input
0 0 1 0 Output Output 2 Input Output
0 0 1 1 Output Output 3 Input Input
0 1 0 0 Output Input 4 Output Output
0 1 0 1 Output Input 5 Output Input
0 1 1 0 Output Input 6 Input Output
0 1 1 1 Output Input 7 Input Input
1 0 0 0 Input Output 8 Output Output
1 0 0 1 Input Output 9 Output Input
1 0 1 0 Input Output 10 Input Output
1 0 1 1 Input Output 11 Input Input
1 1 0 0 Input Input 12 Output Output
1 1 0 1 Input Input 13 Output Input
1 1 1 0 Input Input 14 Input Output
1 1 1 1 Input Input 15 Input Input
82C55A
6
Mode 0 (Basic Input)
Mode 0 (Basic Output)
Mode 0 Configurations
CONTROL WORD #0 CONTROL WORD #2
CONTROL WORD #1 CONTROL WORD #3
tRA
tHR
tRR
tIR
tAR
tRD tDF
RD
INPUT
CS, A1, A0
D7-D0
tAW
tWA
tWB
tWW
tWD
tDW
WR
D7-D0
CS, A1, A0
OUTPUT
1
D7
0D60D50D40D30D20D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D40D30D21D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D40D30D20D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D40D30D21D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
82C55A
7
CONTROL WORD #4 CONTROL WORD #8
CONTROL WORD #5 CONTROL WORD #9
CONTROL WORD #6 CONTROL WORD #10
CONTROL WORD #7 CONTROL WORD #11
Mode 0 Configurations (Continued)
1D70D60D50D41D30D20D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D40D30D20D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D41D30D20D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D40D30D20D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D41D30D21D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D40D30D21D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D50D41D30D21D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D40D30D21D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
82C55A
8
Operating Modes
Mode 1 - (Strobed Input/Output). This functional configura-
tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.
Mode 1 Basic Function Definitions:
• Two Groups (Group A and Group B)
• Each group contains one 8-bit port and one 4-bit
control/data port
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit
port.
Input Control Signal Definition
(Figures 6 and 7)
STB (Strobe Input)
A “low” on this input loads data into the input latch.
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledgment. IBF is set by
STB input being low and is reset by the
rising edge of the
RD input.
CONTROL WORD #12 CONTROL WORD #14
CONTROL WORD #13 CONTROL WORD #15
Mode 0 Configurations (Continued)
1D70D60D51D41D30D20D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D41D30D21D10
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D41D30D20D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
1D70D60D51D41D30D21D11
D0
8
PA7 - PA0
4
PC7 - PC4
4
PC3 - PC0
8
PB7 - PB0
D7 - D0
82C55A
A
B
C
FIGURE 6. MODE 1 INPUT
1D70D61D51D41/0
D3
D2 D1 D0
CONTROL WORD
MODE 1 (PORT A)
PC4
8
IBFAPC5
INTE
A
PA7-PA0
STBA
INTRA
PC3
PC6, PC7
I/O
2
RD
PC6, PC7
1 = INPUT
0 = OUTPUT
1
D7
D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT B)
PC2
8
IBFBPC1
INTE
B
PB7-PB0
STBB
INTRB
PC0
RD
11
82C55A