Intersil Corporation CDP68HC68A2 Datasheet

CDP68HC68A2

July 1998

Features

• 10-Bit Resolution

• 8-Bit Mode for Single Data Byte Transfers

• SPI (Serial Peripheral Interface) Compatible

• Operates Ratiometrically Referencing V
External Source

•14µs 10-Bit Conversion Time

• 8 Multiplexed Analog Input Channels

• Independent Channel Select

• Three Modes of Operation

• On Chip Oscillator

• Low Power CMOS Circuitry

• Intrinsic Sample and Hold

• 16 Lead Dual-In-Line Plastic Package

• 20 Lead Dual-In-Line Small Outline Plastic Package

• Evaluation Board available - CDP68HC05C16BEVAL

DD

or an

Ordering Information

TEMP.RANGE

PART NUMBER

CDP68HC68A2E -40 to 85 16 Ld PDIP E16.3
CDP68HC68A2M -40 to 85 20 Ld SOIC M20.3

(oC) PACKAGE

PKG.

NO.

CMOS Serial 10-Bit A/D Converter

Description

The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive
approximation analog to digital converter (A/D) with a
standard Serial Peripheral Interface (SPI) bus and eight mul­tiplexed analog inputs. Voltage referencing is user selectable
to be relative to either V
analog inputs can range between V

The CDP68HC68A2 employs a switched capacitor,
successive approximation A/D conversion technique which
provides an inherent sample-and-hold function. An onchip
Schmitt oscillator provides the internal timing for the A/D
converter. The Schmitt input can be externally clocked or
connected to a single, external capacitor to form an RC
oscillator with a period of approximately 10-30ns per
picofarad.

Conversion times are proportional to the oscillator period. At
the maximum specified frequency of 1MHz, 10-bit
conversions take 14µs per channel. At the same frequency,
8-bit conversions consume 12µs per channel.

The versatile modes of the CDP68HC68A2 allow any
combination of the eight input channels to be enabled and
any one of the selected channels to be specified as the
“starting” channel. Conversions proceed sequentially
beginning with the starting channel. Nonselected channels
are skipped. Modes can be selected to: sequence from
channel to channel on command; sequence through
channels automatically, converting each channel one time;
or sequence repeatedly through all channels.

The results of 10-bit conversions are stored in 8-bit register
pairs (one pair per channel). The two most significant bits
are stored in the first register of each pair and the eight least
significant bits are stored in the second register of the pair.
To allow faster access, in the 8-bit mode, the results of
conversions are stored in a single register per channel.

or analog channel 0 (AI0). The

DD

and VDD.

SS

A read-only STATUS register facilitates monitoring the
status of conversions. The STATUS register can simply be
polled or the
communications.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

INT pin can be enabled for interrupt dr iven

File Number 1963.3

Pinouts

CDP68HC58A2E

(PDIP)

TOP VIEW

CDP68HC68A2

CDP68HC68A2M

(SOIC)

TOP VIEW

OSC

INT
MISO
MOSI

SCK

CE

AI0 / EXT. REF

V

SS

Block Diagram

SPI CONTROL LOGIC

CE

CONTROL LOGIC

ADDRESS CONTROL

LOGIC

ADDRESS REGISTER

1

16

1
2
3
4
5
6
7
8

4

66

V

DD

15

AI1

14

AI2

13

AI3

12

AI4
AI5

11
10

AI6

9

AI7

ACC LATCH COMPARATOR

8

CONTROL REGISTER

4

CAR

CHOPPER

STABILIZED

COMPARATOR

AI0 / EXT. REF

3

4

4

OSC

INT

2

MISO

3

MOSI

4

NC

5

NC

6

SCK

7
8

CE

9

V

10

SS

STATUS REGISTER

MOSI MISO

DATA REGISTERS (READ ONLY)

SUCCESSIVE APPROXIMATION

SCK

SHIFT REGISTER

A/D CONVERTER LATCH

CONTROL LOGIC

10-BIT CAPACITOR ARRAY

CAPACITOR SWITCH ARRAY

8

8

8

10

V

20

AI1

19

AI2

18

AI3

17

NC

16

NC

15

AI4

14

AI5

13
12

AI6
AI7

11

DD

INTERRUPT

LOGIC

OSCILLATOR

12

INT

OSC

3

STATUS

REGISTERS

CONTROL

REGISTERS

†USED AS VOLTAGE INPUT IN

EXTERNAL REFERENCE MODE.

3

V

SS

V

DD

ANALOG MULTIPLEXER

8

ANALOG INPUTS

AI0

REFERENCE

AI7

2

CDP68HC68A2

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +7V

(Voltage Referenced to VSS Terminal)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Conditions (Note 1)

Temperature Ambient, TA. . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

DC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . .3V Min, 6V Max

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. For maximum reliability, nominal operating conditions should be selected so that operation is always within the ranges specified.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

3. Printed circuit board mount: 58mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Maximum Power Dissipation Per Package (PD)

TA = -40oC to 60oC (Package Type E). . . . . . . . . . . . . . . . 500mW

TA = 60oC to 85oC (Package Type E)

Derate Linearly at . . . . . . . . . . . . . . . . . . .12mW/oC to 200mW

TA = -40oC to 70oC (Package Type M) (Note 3) . . . . . . . . 400mW

TA = -70oC to 85oC (Package Type M) (Note 3)

Derate Linearly at . . . . . . . . . . . . . . . . . . 6.0mW/oC to 310mW

Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . . 40mW

TA = Full Package Temperate Range (All Package Types)

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range (T

Maximum Lead Temperature (During Soldering) . . . . . . . . . . 265oC

At Distance 1/16 ±1/32 In. (1.59 ± 0.79mm)

From Case for 10s Max (SOIC - Lead Tips Only)

) . . . . . -65oC to 150oC

STG

Electrical Specification T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Differential Linearity Error 10-Bit Mode - ±1.25 ±2 LSB
Integral Linear Error 10-Bit Mode - ±1.25 ±2 LSB
Offset Error 10-Bit Mode -1 3 4 LSB
Gain Error 10-Bit Mode -1 1 2 LSB

ANALOG INPUTS: AI0 THRU AI7

Input Resistance In Series with Sample Caps - 85 - Ω
Sample Capacitance During Sample State - 400 - pF
Input Capacitance During Hold State - 20 - pF
Input Current At VIN = V

Input + Full Scale Range From Input RC Time Constant

Input Bandwidth (3dB) - 4.68 - MHz
Input Voltage Range: AI0 3.0 - V

DIGITAL INPUTS: MOSI, SCK, CE, TA = -40oC to 85oC

= 25oC, VDD = 5V, Unless Otherwise Specified.

A

+ During Sample

During Hold or Standby State

VR = 1

REF

- +30 - µA

--±1 µA

V

SS

-V

DD

+0.3

DD

V

V

High Input Voltage V

Low Input Voltage V

Input Leakage --±1 µA
Input Capacitance TA = 25oC--10pF

IH

IL

VDD = 3 to 6V 70 - - % of

V

DD

VDD = 3 to 6V - - 30 % of

V

DD

3

CDP68HC68A2

Electrical Specification T

= 25oC, VDD = 5V, Unless Otherwise Specified. (Continued)

A

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DIGITAL OUTPUTS: MISO, INT, TA = -40oC to 85oC

High Level Output VOH, MISO I
Low Level Output VOL, MISO, INT I
Three-State Output Leakage I

, MISO, INT - - ±10 µA

OUT

SOURCE
SINK

6mA 4.25 - - V

= 6mA - - 0.4 V

TIMING PARAMETERS TA = -40oC to 85oC

Oscillator Frequency f
Conversion Time

(Including Sample Time)

SAMPLE

10-Bit Mode - - -1 MHz
10-Bit Mode 14 Oscillator Cycles

8-Bit Mode 12 Oscillator Cycles
Sample Time (Pre-Encode) 8 Time Constants (8τ) Required First 1.5 Oscillator ≥ 8τ
Serial Clock (SCK) Frequency - - 1.5 MHz
SCK Pulse Width T
MOSI Setup Time T
MOSI Hold Time T

P
DSU
DH

Either SCKA or SCK

B

Prior to Leading Edge of T

After Leading Edge of T

P

150 - - ns

P

60 - - ns

60 - - ns
MISO Rise and Fall Time 200pF Load - - 100 ns
MISO Propagation Delay T
I

DD

I

DD

DOD

From Trailing SCK Edge - - 100 ns
VDD = 5V, Continuous Operation - 1.4 2 mA
VDD = 3V, Continuous Operation - 0.7 1.2 mA

4

CDP68HC68A2

Through this specification the CDP68HC68A2 is referred to
simply as the A2.

Functional Pin Description

OSC - Oscillator (Input/Output)

This pin is user programmable. In the “external” mode, the
clock input for the successive approximation logic is applied
to OSC from an external clock source. The input is a Schmitt
trigger input which provides excellent noise immunity. In the
“internal” mode, a capacitor is connected between this pin
and a power supply to form a “one pin oscillator”. The
frequency of the oscillator is inversely dependent on the
capacitor value. Differences in period, from one device to
another, should be anticipated. Systems utilizing the internal
oscillator must be tolerant of uncertainties in conversion
times or provide trimming capability on the OSC capacitor.
See Table 2 for typical frequencies versus capacitance.

INT - Interrupt (Open Drain Output)

INT is used to signal the completion of an A/D conversion.
This output is generally connected, in parallel with a pullup
resistor, to the interrupt input of the controlling microproces­sor. The open drain feature allows wire-NOR’ing with other
interrupt inputs. The inactive state of
When active,
state of
Select and Status Registers.

MISO - Master-In-Slave-Out (Output)

Serial data is shifted out on this pin. Data is provided most
significant bit first.

MOSI - Master-Out-Slave-In (Input)

Serial data is shifted in on this pin. Data must be supplied
most significant bit first. This is a CMOS input and must be
held high or low at all times to minimize device current.

SCK - Serial Clock (Input)

Serial data is shifted out on MISO, synchronously, with each
leading edge of SCK. Input data from the MOSI pin is
latched, synchronously, with each trailing edge of SCK.

CE - Chip Enable (Input)

An active HIGH device enable. CE is used to synchronize
communications on the SPI lines (MOSI, MISO, and SCK).
When CE is held in a low state, the SPI logic is placed in a
reset mode with MISO held in a high impedance state.
Following a transition from low to high on CE, the
CDP68HC68A2 interprets the first byte transferred on the
SPI lines as an address. If CE is maintained high,
subsequent transfers are interpreted as data reads or writes.

AIO/

EXT REF - Analog Input 0/External Reference (Input)

This input is one of eight analog input channels. Its function
is selectable through the Mode Select Register (MSR). If VR
is set high in the MSR, AI0/
voltage reference against which all other inputs are

INT is driven to a low level output voltage. The

INT is controlled and monitored by bits in the Mode

EXT REF provides an external

INT is high impedance.

measured. AI0/EXT REF must fall within the VSSand V
supply rails. If VR is set low in the MSR, VDDis used as the
reference voltage and AI0/
analog input (see AI1-AI7).

AI1-AI7 - Analog Inputs 1-7 (Inputs)

Together with AI0/
analog inputs (channels) which are multiplexed within the
CDP68HC68A2 to a single, high-speed, successive approxi­mation, A/D converter. AI1-AI7 must fall within the V
V

supply rails.

DD

V

- Negative Power Supply

SS

This pin provides the negative analog reference and the
negative power supply for the CDP68HC68A2.

V

- Positive Power Supply

DD

This pin provides the positive power supply and, depending
on the value of the VR bit in the MSR, the positive analog
reference for the CDP68HC68A2.

EXT REF, these pins provide the eight

EXT REF is treated as any other

SS

DD

and

Overview

From the programmer’s perspective, the A2 is comprised of
three control registers (Mode Select Register - MSR,
Channel Select Register - CSR, and Starting Address
Register - SAR), a status register (SR), an array of eight
pairs of Data Registers, and one non-addressable, internal
register (Channel Address Register). See Figure 1.

The A2 contains a high speed, 10-bit, successive
approximation, analog to digital converter (A/D). The input to
the A/D can be any one of the A2’s eight analog inputs (AI0
through AI7). The contents of the CAR determine which ana­log input is connected to the A/D. The result of each analog
to digital conversion is written to the Data Register array. The
Data Register array is also addressed by the contents of the
CAR, providing a one to one correspondence between each
analog input and each Data Register pair.

The contents of the CAR are also used during Data Register
reads to address the Data Register array. The CAR is
automatically jammed with the correct address when an
Address/Control Byte is sent to the A2. A second means, to
initialize the CAR, is by writing to the SAR.

Normal procedure for programming the A2 is to first select
the desired hardware mode by writing to the MSR. The
“active” analog channels are then specified by writing to the
CSR (channels not selected in the CSR are skipped during
conversions and burst mode reads). Finally, a write to the
SAR initializes the CAR (designating the first channel to
convert) and initiates the A/D conversions.

Polling of the SR or hardware interrupts can be used to
determine the completion of conversions.

The converted data is read from the data registers. In eight
bit mode, a single register is read for each channel of inter­est. In ten bit mode, two registers are read per channel.

5