March 1997
CDP1881C,
CDP1882, CDP1882C
CMOS 6-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder
Functions Multiplexed or Non-Multiplexed
• Decodes Up to 16K Bytes of Memory
• Interfaces Directly with CDP1800-Series Microprocessors at Maximum Clock Frequency
• Can Replace CDP1866 and CDP1867 (Upward Speed
and Function Capability)
Ordering Information
TEMP.
RANGE
PACKAGE 5V 10V
PDIP CDP1881CE - -40 to +85 E20.3
PDIP CDP1882CE - -40 to +85 E18.3
PDIP
Burn-In
SBDIP - CDP1882D -40 to +85 D18.3
CDP1882CEX - -40 to +85 E18.3
(oC)
PKG.
NO.
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit
memory latch and decoder circuits intended for use in
CDP1800 series microprocessor systems. They can interface directly with the multiplexed address bus of this system
at maximum clock frequency, and up to four 4K x 8-bit memories to provide a 16K byte memory system. With four 2K x
8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock input
to V
, the latches are in the data-following mode and the
DD
decoded outputs can be used in general purpose memorysystem applications.
The CDP1881C, CDP1882 and CDP1882C are intended for
use with 2K or 4K byte RAMs and are identical except that in
the CDP1882
The CDP1882 is functionally identical to the CDP1882C. It
differs in that the CDP1882 has recommended operating
voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V.
The CDP1881C, CDP1882 and CDP1882C are supplied in
20 lead and 18 lead packages, respectively. The
CDP1881C is supplied only in a dual-in-line plastic package (E suffix). The CDP1882 is supplied in dual-in-line,
hermetic side-brazed ceramic (D suffix) and in plastic (E
suffix) packages.
MWR and MRD are excluded.
Pinouts
CDP1881C
(PDIP)
TOP VIEW
MA5
MA4
MA3
MA2
MA1
MA0
MRD
MWR
V
1
2
3
4
5
6
7
8
9
10
SS
| Copyright © Intersil Corporation 1999
CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
20
V
DD
19
A8
18
A9
17
A10
16
A11
15
CS0
14
CS1
13
CS2
12
CS3
CE
11
4-1
CDP1882, CDP1882C
(PDIP, CERDIP)
TOP VIEW
CLOCK
MA5
MA4
MA3
MA2
MA1
MA0
CE
V
1
2
3
4
5
6
7
8
9
SS
18
V
DD
17
A8
16
A9
15
A10
14
A11
13
CS0
12
CS1
11
CS2
10
CS3
File Number 1367.2
CDP1881C, CDP1882, CDP1882C
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1881C and CDP1882C. . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
18 Lead PDIP . . . . . . . . . . . . . . . . . . . 85 N/A
20 Lead PDIP . . . . . . . . . . . . . . . . . . . 80 N/A
SBDIP Package. . . . . . . . . . . . . . . . . . 85 22
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mW
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Storage Temperature Range (T
) . . . . . . . . . . . .-65oC to +150oC
STG
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions At T
= Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
CDP1882 CDP1881C, CDP1882C
PARAMETER
DC Operating Voltage Range 4 10.5 4 6.5 V
Input Voltage Range V
Static Electrical Specifications At T
= -40oC to +85oC, VDD± 5%, Except as Noted:
A
SS
V
DD
V
SS
V
DD
CONDITIONS CDP1882 CDP1881C, CDP1882C
PARAMETER SYMBOL
Quiescent Device
V
O
(V)
I
DD
- 0, 5 5 - 1 10 - 5 50 µA
V
(V)
V
IN
DD
(V) MIN
(NOTE 1)
TYP MAX MIN
(NOTE 1)
TYP MAX
Current
- 0, 10 10 - 10 100 - - - µA
Output Low Drive
I
OL
0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA
(Sink) Current
0.5 0, 10 10 3.2 6.4 - - - - mA
Output High Drive
I
OH
4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - mA
(Source) Current
9.5 0, 10 10 -2.3 -4.6 - - - - mA
UNITSMIN MAX MIN MAX
V
UNITS
Output Voltage
Low-Level (Note 2)
Output Voltage
High-Level (Note 2)
Input Low Voltage V
Input High Voltage V
V
OL
- 0, 5 5 - 0 0.1 - 0 0.1 V
- 0, 10 10 - 0 0.1 - - - V
V
OH
- 0, 5 5 4.9 5 - 4.9 5 - V
- 0, 10 10 9.9 10 - - - - V
0.5, 4.5 - 5 - - 1.5 - - 1.5 V
IL
1, 9 - 10 - - 3 - - - V
0.5, 9.5 - 5 3.5 - - 3.5 - - V
IH
1, 9 - 10 7 - - - - - V
4-2
CDP1881C, CDP1882, CDP1882C
Static Electrical Specifications At T
= -40oC to +85oC, VDD± 5%, Except as Noted: (Continued)
A
CONDITIONS CDP1882 CDP1881C, CDP1882C
PARAMETER SYMBOL
Input Leakage Current I
V
O
(V)
IN
Any
V
(V)
V
IN
DD
(V) MIN
(NOTE 1)
TYP MAX MIN
(NOTE 1)
TYP MAX
UNITS
0, 5 5 - - ±1- - ±1 µA
Input
0, 10 10 - - ±2- - -µA
Operating Current
I
DD1
0, 5 0, 5 5 - - 2 - - 2 mA
(Note 2)
0, 10 0, 10 10 - - 4 - - - mA
Input Capacitance C
Output Capacitance C
Minimum Data
V
IN
OUT
DR
- - - - 5 7.5 - 5 7.5 pF
- - - - 10 15 - 10 15 pF
VDD = V
DR
- 2 2.4 - 2 2.4 V
Retention Voltage
Data Retention Current I
DR
VDD = 2.4V - 0.01 1 - 0.5 5 µA
NOTES:
1. Typical values are for TA = +25oC.
2. IOL = IOH = 1µA.
3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuits (equivalent to typical CDP1800
system at 3.2MHz, 5V; and 6.4MHz, 10V).
MA0
MA1
MA2
MA3
MA4
MA5
CLOCK
MRD
MWR
CE
7
6
5
4
3
2
1
8
9
11
DCQ
DCQ
DCQ
DCQ
DCQ
Q
DCQ
Q
V
V
DD
SS
19
A8
18
A9
17
A10
16
A11
15
CS0
14
CS1
13
CS2
12
CS3
20
=
10
=
CLOCK
MA0
MA1
MA2
MA3
MA4
MA5
CE
7
6
5
4
3
2
1
8
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
17
A8
A9
16
15
A10
14
A11
13
CS0
Q
12
CS1
Q
V
V
DD
11
CS2
10
CS3
18
=
9
=
SS
FIGURE 1. FUNCTIONAL DIAGRAM FOR THE CDP1881C FIGURE 2. FUNCTIONAL DIAGRAM FOR THE CDP1882,
CDP1882C
4-3