Intersil Corporation CDP1878C Datasheet

CDP1878C

March 1997

Features

• Compatible with General Purpose and CDP1800
Series Microprocessor Systems

• Two 16-Bit Down Counters and Two 8-Bit Control
Registers

• 5 Modes Including a Versatile Variable-Duty Cycle
Mode

• Programmable Gate-Level Select

• Two-Complemented Output Pins for Each Counter­Timer

• Software-Controlled Interrupt Output

• Addressable in Memory Space or CDP1800-Series I/O
Space

Ordering Information

PART

NUMBER TEMP. RANGE PACKAGE PKG. NO.

CDP1878CE -40oC to +85oC PDIP E28.6

CDP1878CD -40oC to +85oC SBDIP N28.6

CMOS Dual Counter-Timer

Description

The CDP1878C is a dual counter-timer consisting of two 16­bit programmable down counters that are independently
controlled by separate control registers. The value in the reg­isters determine the mode of operation and control func­tions. Counters and registers are directly addressable in
memory space by any general industry type microproces­sors, in addition to input/output mapping with the CDP1800
series microprocessors.

Each counter-timer can be configured in five modes with the
additional flexibility of gate-level control. The control regis­ters in addition to mode formatting, allow software start and
stop, interrupt enable, and an optional read control that
allows a stable readout from the counters. Each counter­timer has software control of a common interrupt output with
an interrupt status register indicating which counter-timer
has timed out.

In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.

This type is supplied in 28-lead dual-in-line ceramic pack­ages (D suffix), and 28-lead dual-in-line plastic packages (E
suffix).

Pinout

IO/
TPB/

INT
TAO
TAO
TAG

TACL

MEM

WR
TPA

V

RD

CS

A0
A1
A2

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14

CDP1878C

(DIP)

TOP VIEW

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

DD

DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
TBO
TBO
TBG
TBCL
RESET

TABLE 1. MODE DESCRIPTION

MODE FUNCTION APPLICA TION

1 Timeout Outputs change when clock

decrements counter to “0”

2 Timeout

Strobe

3 Gate-Con-

trolled One
Shot

4 Rate Generator Repetitive clockwide output

5 Variable-Duty

Cycle

One clockwide output pulse
when clock decrements
counter to “0”

Outputs change when clock
decrements counter to “0”.
Retriggerable

pulse

Repetitive output with
programmed duty cycle

Event counter

Trigger pulse

Time-delay
generation

Time-base
generator

Motor control

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

4-91

File Number 1341.2

CDP1878C

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range, (VDD)

(All Voltages Referenced to VSSTerminal)

CDP1878C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 55 N/A

SBDIP Package. . . . . . . . . . . . . . . . . . 50 12

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range

(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

Operating Temperature Range (TA)

Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Storage Temperature Range (T

). . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Recommended Operating Conditions At T

= Full Package Temperature Range. For maximum reliability, operating conditions

A

should be selected so that operation is always within the following ranges:

PARAMETER SYMBOL MIN MAX UNITS

DC Operating Voltage Range 4 6.5 V
Input Voltage Range V
Maximum Clock Input Rise or Fall Time tR, t
Minimum Clock Pulse Width tWL, t
Maximum Clock Input Frequency f

Static Electrical Specifications At T

= -40oC to +85oC, VDD± 5% Except as noted:

A

F

WH

CL

SS

-5µs

200 - ns

DC 1 MHz

V

DD

V

CONDITIONS LIMITS

PARAMETER SYMBOL

Quiescent Device Current I
Output Low Drive (Sink) Current I
Output High Drive (Source) Current I
Output Voltage Low-Level (Note 2) V
Output Voltage High-Level (Note 2) V
Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Operating Current (Note 3) I
Input Capacitance C
Output Capacitance C

DD

OL

OH

OL

OH

IL

IH

IN

DD1

IN

OUT

V

O

(V)

- 0, 5 5 - 0.02 200 µA

0.4 0, 5 5 1.6 3.2 - mA

4.6 0, 5 5 -1.15 -2.3 - mA

- 0, 5 5 - 0 0.1 V

- 0, 5 5 4.9 5 - V

0.5, 4.5 - 5 - - 1.5 V

0.5, 9.5 - 5 3.5 - - V

Any Input 0, 5 5 - - ±1 µA

- 0, 5 5 - 1.5 3 mA

---- 57.5pF

----1015pF

V
(V)

IN

V

DD

(V) MIN

(NOTE 1)

TYP MAX

UNITS

NOTES:

1. Typical values are for TA = +25oC and nominal VDD.

2. IOL = IOH = 1µA

3. Operating current measured at 200kHz for VDD = 5V, with open outputs (worst-case frequencies for CDP1802A system operating at max­imum speed of 3.2MHz).

4-92

Functional Diagram

CDP1878C

JAM

REGISTER A

8-BIT

EXTERNAL

BUS

RESET

TPB/WR

IO/MEM

V

DD

V

SS

RD

TPA

CS

A2
A1
A0

I-O

CONTROL

AND

LOGIC

DAT A

BUS

DRIVERS

COUNTER A

HOLDING

REGISTER A

JAM

REGISTER B

COUNTER B

HOLDING

REGISTER B

CONTROL REGISTER A

AND MODE CONTROL

INT AND

STATUS REGISTER

CONTROL REGISTER B

AND MODE CONTROL

GATE A

TAO
TAO

CLOCK A

INT

GATE B

TBO
TBO

CLOCK B

FUNCTIONAL DEFINITIONS FOR CDP1878C TERMINALS

TERMINAL USAGE TERMINAL USAGE

VDD - V

Power TAO, TAO Complemented outputs of Timer A

SS

DB0-DB7 Data to and from device TBO, TBO Complemented outputs of Timer B

TPB/WR, RD Directional Control Signals TPA Used with CDP1800-series processors, tied high

otherwise

A0, A1, A2 Addresses that select counters or registers CS Active high input that enables device

TACL, TBCL Clocks used to decrement counters INT Low when counter is “0”

TAG, TBG Gate inputs that control counters RESET When active, TAO, TBO are low, TAO, TBO are

high. Interrupt status register is cleared.

IO/MEM Tied high in CDP1800 input/output mode, other-

wise tied low

4-93

CDP1878C

REGISTER TRUTH TABLE

ADDRESS ACTIVE

REGISTER COUNTERA2 A1 A0 TPB/WR RD

1 1 0 X Write Counter A MSB
1 1 0 X Read Counter A MSB
0 1 0 X Write Counter A LSB
0 1 0 X Read Counter A LSB
1 0 0 X Control Register A
1 1 1 X Write Counter B MSB
1 1 1 X Read Counter B MSB
0 1 1 X Write Counter B LSB
0 1 1 X Read Counter B LSB
1 0 1 X Control Register B
1 0 0 X Interrupt Status Register
101 X
0 0 0 Not Used
0 0 1 Not Used

Programming Model

BUS 7

CONTROL REGISTER

WRITE ONLY

HOLDING REGISTER LSB

READ ONLY

HOLDING REGISTER MSB

COUNTER A REGISTERS COUNTER B REGISTERS

BUS 0

JAM REGISTER LSB

WRITE ONLY

JAM REGISTER MSB

HOLDING REGISTER LSB

READ ONLY

HOLDING REGISTER MSB

BUS 7

XX000000

READ ONLY

BUS 0

BUS 7

CONTROL REGISTER

WRITE ONLY

BUS 0

JAM REGISTER LSB

WRITE ONLY

JAM REGISTER MSB

TIMER A
TIMER B

INTERRUPT STATUS REGISTER

4-94