Intersil Corporation CDP1877C, CDP1877 Datasheet

CDP1877,

CDP1877C

March 1997

Features

• Compatible with CDP1800 Series

• Programmable Long Branch V ector Address and
Vector Interval

• 8 Levels of Interrupt Per Chip

• Easily Expandable

• Latched Interrupt Requests

• Hard Wired Interrupt Priorities

• Memory Mapped

• Multiple Chip Select Inputs to Minimize Address
Space Requirements

Ordering Information

TEMP.

PACKAGE

PDIP -40oC to

RANGE 5V 10V

CDP1877CE CDP1877E E28.6

+85oC

PKG.

NO.

Programmable Interrupt Controller (PIC)

Description

The CDP1877 and CDP1877C are programmable 8-level interrupt control­lers designed for use in CDP1800 series microprocessor systems. They
provide added versatility by extending the number of permissible interrupts
from 1 to N in increments of 8.

When a high to low transition occurs on any of the PIC interrupt lines (
IR7), it will be latched and, unless the request is masked, it will cause the
INTERRUPT line on the PIC and consequently the INTERRUPT input on
the CPU to go low.

The CPU accesses the PIC by having interrupt vector register R(1) loaded
with the memory address of the PIC. After the interrupt S3 cycle, this regis­ter value will appear at the CPU address bus, causing the CPU to fetch an
instruction from the PIC. This fetch cycle clears the interrupt request latch
bit to accept a new high-to-low transition, and also causes the PIC to issue a
long branch instruction (CO) followed by the preprogr ammed v ector address
written into the PIC’s address registers, causing the CPU to branch to the
address corresponding to the highest priority active interrupt request.

If no other unmasked interrupts are pending, the
PIC will return high. When an interrupt is requested on a masked interrupt
line, it will be latched but it will not cause the PIC
low. All pending interrupts, masked and unmasked, will be indicated by a “1”
in the corresponding bit of the status register. Reading of the status register
will clear all pending interrupt request latches.

Several PICs can be cascaded together b y connecting the
put of one chip to the
vides 8 additional interrupt levels to the system. The number of units
cascadable depends on the amount of memory space and the extent of the
address decoding in the system.

Interrupts are prioritized in descending order;
has the lowest priority.

The CDP1877 and CDP1877C are functionally identical. They differ in that
the CDP1877 has a recommended operating voltage range of 4V to 10.5V,
and the CDP1877C has a recommended operating voltage range of 4V to

6.5V.

CASCADE input of another. Each cascaded PIC pro-

INTERRUPT output of the

INTERRUPT output to go

INTERRUPT out-

IR7 has the highest and IR0

IR0 to

Pinout

CDP1877, CDP1877C (PDIP)

TOP VIEW

V

CASCADE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0

TPA

TPB

MWR

MRD

V

1
2
3
4
5
6
7
8

9
10
11
12
13
14

SS

28

DD

BUS 7

27

BUS 6

26

BUS 5

25
24

BUS 4

23

BUS 3
BUS 2

22
21

BUS 1

20

BUS 0
CS/Ax

19
18

CS/Ay

17

CS

16

CS
INT

15

| Copyright © Intersil Corporation 1999

Programming Model

PROGRAMMABLE INTERRUPT CONTROLLER (PIC)

BUS 7 BUS 0

PAGE REGISTER WRITE

A15 A14 A13 A12 A11 A10 A9 A8

BUS 7 BUS 0

CONTROL REGISTER WRITE

B7 B6 B5 B4 B3 B2 B1 B0

BUS 7 BUS 0

MASK REGISTER WRITE

M7 M6 M5 M4 M3 M2 M1 M0

BUS 7 BUS 0

STATUS REGISTER READ

S7 S6 S5 S4 S3 S2 S1 S0

BUS 7 BUS 0

POLLING REGISTER READ

P7 P6 P5 P4 P3 P2 P1 P0

4-82

File Number

ONLY

ONLY

ONLY

ONLY

ONLY

1319.2

CDP1877, CDP1877C

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range, (VDD)

(All Voltages Referenced to VSSTerminal)

CDP1877. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V

CDP1877C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range

(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

Operating Temperature Range (TA)

Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Storage Temperature Range (T

) . . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Static Electrical Specifications At T

= -40 to +85oC, VDD±5%, Unless Otherwise Specified

A

CONDITIONS LIMITS

CDP1877 CDP1877C

PARAMETER

Quiescent Device
Current

Output Low Drive (Sink)
Current

Output High Drive
(Source) Current

Output Voltage Low Level
(Note 2)

Output Voltage High Level
(Note 2)

Input Low Voltage V

V

O

(V)

I

DD

- 0, 5 5 - 0.01 50 - 0.02 200 µA

- 0, 10 10 - 1 200 - - - µA

I

OL

0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA

0.5 0, 10 10 2.6 5.2 - - - - mA

I

OH

4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - mA

9.5 0, 10 10 -2.6 -5.2 - - - - mA

V

OL

- 0, 5 5 - 0 0.1 - 0 0.1 V

- 0, 10 10 - 0 0.1 - - - V

V

OH

- 0, 5 5 4.9 5 - 4.9 5 - V

- 0, 10 10 9.9 10 - - - - V

0.5, 4.5 - 5 - - 1.5 - - 1.5 V

IL

V
(V)

V

IN

(V)

DD

MIN

(NOTE1)

TYP MAX MIN

(NOTE1)

TYP MAX

0.5, 9.5 - 10 - - 3 - - - V

Input High Voltage V

0.5, 4.5 - 5 3.5 - - 3.5 - - V

IH

0.5, 9.5 - 10 7 - - - - - V

Input Leakage Current I

Three-State Output
Leakage Current

Operating Device Current

I

(Note 3)

Input Capacitance C
Output Capacitance C

IN

I

OUT

OPER

OUT

Any

Input

0, 5 5 - - ±1- - ±1 µA

0, 10 10 - - ±2- - -µA

0, 5 0, 5 5 - ±10

0, 10 0, 10 10 - ±10

- - 5 - 0.5 1.0 - 0.5 1.0 mA

- - 10 - 1.9 3.0 - - - mA

IN

- - - - 5 7.5 - 5 7.5 pF

- - - - 10 15 - 10 15 pF

-4

±1-±10

-4

±10 - - - µA

-4

±1 µA

NOTES:

1. Typical values are for TA = +25oC and nominal VDD.

2. IOL = IOH = 1µA

3. Operating current is measured under worst-case conditions in a 3.2MHz CDP1802A system, one PIC access per instruction cycle.

UNITS

4-83

CDP1877, CDP1877C

Operating Conditions At T

= Full package temperature range. F or maximum reliability, operating conditions should be selected so

A

that operation is always within the following ranges:

LIMITS

CDP1877 CDP1877C

PARAMETER

MIN MAX MIN MAX

DC Operating Voltage Range 4 10.5 4 6.5 V
Input Voltage Range V

TPA

CA/A

CA/A

CASC

CS
CS

4-BIT

X

Y

LATCH

READ

STATUS

REGISTER

TPB

MWR

MRD

WRITE

MASK

REGISTER

DECODER

CS

SS

V

DD

WRITE PAGE REGISTER
WRITE CONTROL REGISTER
WRITE MASK REGISTER
READ STATUS REGISTER
READ POLLING REGISTER

READ LONG BRANCH

INT

WRITE

PAGE

REGISTER

READ
LONG

BRANCH

V

SS

V

DD

UNITS

V

IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0

EN CLEAR

INTERRUPT

LATCH/

STATUS

REGISTER

CLEAR

EN

HIGH

VECTOR

ADDRESS

READ POLLING

REGISTER

LOW

VECTOR

ADDRESS

UPPER BITS

MASK

REGISTER

CLEAR

PRIORITY

ENCODER/

VECTOR

ADDRESS

GENERATION

INTERVAL

CONTROL REGISTER

FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1877

EN

EN

LONG

BRANCH

INSTRUCTION

GENERATE

LOGIC

WRITE
CONTROL
REGISTER

MWR MRD

DAT A

BUS

BUFFERS

BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7

4-84