Intersil Corporation CDP1875C, CDP1874C, CDP1872C Datasheet

CDP1872C,

CDP1874C, CDP1875C

March 1997

Features

• Parallel 8-Bit Input/Output Register with Buffered Out­puts

• High-Speed Data-In to Data-Out 85ns (Max) at V

• Flexible Applications In Microprocessor Systems as
Buffers and Latches

• High Order Address-Latch Capability in CDP1800­Series Microprocessor Systems

• Output Sink Current = 5mA (Min) at V

DD

= 5V

• Three-State Output - CDP1872C and CDP1874C

Ordering Information

PART

NUMBER TEMP. RANGE PACKAGE

CDP1872CE -40oC to +85oC PDIP E22.4
CDP1874CE -40oC to +85oC PDIP E22.4
CDP1875CE -40oC to +85oC PDIP E22.4

High-Speed 8-Bit Input and Output Ports

Description

The CDP1872C, CDP1874C and CDP1875C devices are
high-speed 8-bit parallel input and output ports designed for

DD

PKG.

= 5V

NO.

use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.

These devices have flexible capabilities as buffers and data
latches and are reset by

CLR input when the data strobe is

not active.
The CDP1872C and CDP1874C are functionally identical

except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.

The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.

Pinouts

CS1

DI0

DO0

DI1

D01

DI2

D02

DI3

D03

CLOCK

V

SS

CDP1872C INPUT PORT

(PDIP)

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

CDP1874C INPUT PORT

(PDIP)

TOP VIEW

22

V

DD

21

DI7

20

D07

19

DI6

18

D06

17

DI5

16

D05

15

DI4

14

D04

13

CLR

12

CS2

CLOCK

CS1

DI0

DO0

DI1

D01

DI2

D02

DI3

D03

V

1

2

3

4

5

6

7

8

9

10

11

SS

22

V

DD

21

DI7

20

D07

19

DI6

18

D06

17

DI5

16

D05

15

DI4

14

D04

13

CLR

12

CS2

CDP1875C OUTPUT PORT

(PDIP)

TOP VIEW

1

CS1

2

DI0

3

DO0

4

DI1

5

D01

6

DI2

7

D02

8

DI3

9

D03

10

CS3

11

V

SS

22

V

DD

21

DI7

20

D07

19

DI6

18

D06

17

DI5

16

D05

15

DI4

14

D04

13

CLR

12

CS2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

4-76

File Number

1255.2

CDP1872C, CDP1874C, CDP1875CCDP1872C, CDP1874C, CDP1875C

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, (VDD). . . . . . . . . . . . . . . . . -0.5V to +7V

(Voltage referenced to VSS Terminal)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range

(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

Operating Temperature Range (TA)

Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Storage Temperature Range (T

) . . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Recommended Operating Conditions At T

= -40 to +85oC. For maximum reliability, operating conditions should be selected

A

so that operation is always within the following ranges:

LIMITS

PARAMETER

ALL TYPES UNITS

DC Operating-Voltage Range 4 to 6.5 V

Input Voltage Range VSS to V

Static Electrical Specifications At T

= -40 to +85oC, VDD±5%, Unless Otherwise Specified.

A

DD

LIMITS

PARAMETER

Quiescent Device Current I
Output Low Drive (Sink)

TEST CONDITIONS

V

O

(V)

DD

I

OL

-0, 55 - 2550µA

0.4 0, 5 5 5 10 - mA

V
(V)

IN

V

DD

(V) MIN

ALL TYPES

(NOTE 1)

TYP MAX

Current
Output High Drive (Source)

I

OH

4.6 0, 5 5 -4 -7 - mA

Current
Output Voltage Low-Level

V

OL

- 0, 5 5 - 0 0.1 V

(Note 2)

V

UNITS

Output Voltage High-Level

V

OH

- 0, 5 5 4.9 5 - V

(Note 2)
Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Three-State Output Leakage

I

OUT

IN

0.5, 4.5 - 5 - - 1.5 V

IL

0.5, 4.5 - 5 3.5 - - V

IH

- 0, 5 5 - - ±1 µA

0, 5 0, 5 5 - - ±5 µA

Current (Note 3)
Input Capacitance C
Output Capacitance (Note 3) C

IN

OUT

----15-pF

----15-pF

NOTES:

1. Typical values are for TA = +25oC and nominal VDD±5%.

2. IOL = IOH = 1µA

3. For CDP1872C and CDP1874C only.

4-77