Intersil Corporation CDP1871AC, CDP1871A Datasheet

REFERENCE APP NOTE 7374

August 1996

CDP1871A,

CDP1871AC

CMOS Keyboard Encoder

Features

• Directly Interfaces with CDP1800-Series Microprocessor

• Low Power Dissipation

• Three-State Outputs

• Scans and Generates Code for 53 Key ASCII Ke yboar d Plus
32 HEX Keys (SPST Mechanical Contact Switches)

• Shift, Control, and Alpha Lock Input

• RC-Controlled Debounce Circuitry

• Single Supply 4V to 10.5V. . . . . . . . . . . . . (CDP1871A)

4V to 6.5V. . . . . . . . . . . . . (CDP1871AC)

• N-Key Lockout

Ordering Information

PKG.

PACKAGE TEMP. RANGE 5V 10V

PDIP -40oC to +85oC CDP1871ACE CDP1871AE E40.6
PLCC -40oC to +85oC CDP1871ACQ - N44.65
SBDIP -40oC to +85oC CDP1871ACD CDP1871AD D40.6

Burn-In CDP1871ACDX - D40.6

NO.

Description

The CDP1871A is a keyboard encoder designed to
directly interface between a CDP1800-series micro­processor and a mechanical keyboard array, providing
up to 53 ASCII coded keys and 32 HEX coded keys,
as shown in the system diagram (Figure 1).

The keyboard may consist of simple single-pole
single-throw (SPST) mechanical switches. Inputs are
provided for alpha-lock, control, and shift functions,
allowing 160 unique codes. An external R-C input is
available for user-selectable debounce times. The N­key lock-out feature prevents unwanted key codes if
two or more keys are pressed simultaneously.

The CDP1871A and CDP1871AC are functionally
identical. They differ in that the CDP1871A has a
recommended operating voltage range of 4V to 10.5V,
and the CDP1871AC has a recommended operating
voltage range 4V to 6.5V. These types are supplied in
40 lead dual-in-line ceramic packages (D suffix), and
40 lead dual-in-line plastic packages (E suffix), and 44
lead plastic chip-carrier packages (Q suffix).

Pinouts

40 LEAD PDIP, CERDIP

TOP VIEW

V

1

D1
D2

2
3

D3
D4

4
5

D5

6

D6

7

D7

8

D8

9

D9

10

D10

11

D11

12

S1

13

S2

14

S3

15

S4

16

S5

17

S6

18

S7

19

S8

V

20

SS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

40

DD

39

SHIFT

38

CONTROL

37

ALPHA

36

DEBOUNCE

35

RTP

34

TPB

33

DA

32

BUS 7

31

BUS 6

30

BUS 5

29

BUS 4

28

BUS 3

27

BUS 2

26

BUS 1

25

BUS 0

24

CS4

23

CS3

22

CS2
CS1

21

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D5
D6
D7
D8
D9
D10
D11
S1
S2
S3
S4

NC

7
8
9
10
11
12
13
14
15
16
17

S5S6S7

44 LEAD PLCC

(Q Suffix) TOP VIEW

DD

D4D3D2D1V

20 21 22 23 24 25 261918

S8

SHIFT

44 43 42 41 40

123456

CS1

CS2

VSS

CONTROL

CS3

ALPHA

DEBOUNCE

CS4

BUS 0

NC

39
38
37
36
35
34
33
32
31
30
29

2827

NC

File Number

RPT
TPB
DA
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
NC

1374.2

CDP1871A, CDP1871AC

V

DD

0.1µF

100K

CDP1800-SERIES

CPU

BUS0-BUS7

36

11

D11

UP TO 11 SETS

OF 8 SWITCHES EACH

N0-N2

MRD

TPB

CONTROL

40

CS1,
CS2,
CS3

CS4

TPB

DEBOUNCE

21

23

24
34

CDP1871A

V

DD

SHIFT

39

SHIFT

D1

1

CONTROL

38

ALPHA LOCK

37

NORMAL

CONTROL

ALPHA

BUS0-BUS7

S1
S2
S3
S4
S5
S6
S7
S8

12
13
14
15
16
17
18
19

3225

8 BIT DATA BUS

FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A

CS1

CS2
CS3
CS4

TPB

DA

RPT

R

X

C

X

21
22
23
24
34

V

DD

DEBOUNCE

33

35

CS

SCAN CLOCK

THREE-STAGE

SCAN COUNTER

FIVE-STAGE

SCAN COUNTER

BUS ENABLE

CONTROL

LOGIC

KEY

DETECT

F/F

C1-C3

C4-C8

THREE-STATE

OUTPUT

BUFFERS

25

32

BUS 0

BUS 7

36

R

N

STATUS

LATCHES

KEY DOWN

DETECT

PD

KEY BOARD

12

SENSE

FROM

LINES

1 OF 8

MUXR

LATCH

R

PD

19

II

DECODER/

DRIVERS

TO

KEY BOARD

1 11

DRIVE

DI DII

LINES

37

ALPHA

R

PD

39

SHIFT38CONTROL

40

V

DD

V

SS

20

R

PD

FIGURE 2. CDP1871A BLOCK DIAGRAM

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CDP1871A, CDP1871AC

Absolute Maximum Ratings Thermal Information

(All Voltages Referenced to VSSTerminal)

CDP1871A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V

CDP1871AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 60 N/A

PLCC Package . . . . . . . . . . . . . . . . . . 50 N/A

SBDIP Package. . . . . . . . . . . . . . . . . . 60 18

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range

(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

Operating Temperature Range (TA)

Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Storage Temperature Range (T

) . . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Recommended Operating Conditions At T

= -40 to +85oC. For maximum reliability, operating conditions should be selected

A

so that operation is always within the following ranges:

LIMITS

CDP1871AD, CDP1871AE CDP1871ACD, CDP1871ACE

V

PARAMETER

(V)

DD

MIN MAX MIN MAX

Supply Voltage Range 4 10.5 4 6.5 V

Recommended Input Voltage

V

SS

V

DD

V

SS

V

DD

Range

Clock Input Frequency, TPB

f

CL

5 DC 0.4 DC 0.4 MHz

(Keyboard Capacitance = 200 pF)

10 DC 0.8 - - MHz

NOTE:

1. Printed-circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.

Static Electrical Specifications At T

= -40 to +85oC, Unless Otherwise Specified

A

CONDITIONS LIMITS

CDP1871AD
CDP1871AE

CDP1871ACD
CDP1871ACE

UNITS

V

PARAMETER

Quiescent Device
Current

Output Low Drive (Sink)
Current (Except Debounce
and D1-D11)

Debounce I

D1-D11 I

V

O

(V)

I

DD

- 0.5 5 - 0.1 50 - 1 200 µA

V
(V)

V

IN

DD

(V)

MIN

(NOTE 1)

TYP MAX MIN

(NOTE1)

TYP MAX

UNITS

- 0, 10 10 - 1 200 - - - µA

I

OL

0.4 0, 5 5 0.5 1 - 0.5 1 - mA

0.5 0, 10 10 1 2 - - - - mA

OL

0.4 0, 5 5 0.75 1.5 - 0.75 1.5 - mA

0.5 0, 10 10 1 2 - - - - mA

OL

0.4 0, 5 5 0.05 0.1 - 0.05 0.1 - mA

0.5 0, 10 10 0.1 0.2 - - - - mA

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