Intersil Corporation CDP1853C-3 Datasheet
CDP1853C/3
March 1997
Features
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Microprocessor
• CHIP ENABLE (CE) Allows Easy Expansion for Multilevel I/O Systems
Ordering Information
PACKAGE TEMP. RANGE 5V 10V
SBDIP -55oC to +125oC CDP1853CD3 - D16.3
High-Reliability CMOS N-Bit 1 of 8 Decoder
Description
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a recommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
PKG.
NO.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
CLK A
N0
N1
OUT 0
OUT 1
OUT 2
OUT 3
V
SS
16 LEAD SBDIP
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK B
N2
CE
OUT 4
OUT 5
OUT 6
OUT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Copyright © Intersil Corporation 1999
4-40
File Number
1713.2
CDP1853/3, CDP1853C/3
CDP1853/3 Functional Diagram
2
N0
CE
CLOCK
A
(TPA)
CLOCK
B
(TPB)
3
N1
14
N2
13
1
15
FIGURE 1.
1 OF 8
DECODER
EN
QN
TRUTH TABLE
4
OUT 0
5
OUT 1
6
OUT 2
7
OUT 3
12
OUT 4
11
OUT 5
10
OUT 6
9
OUT 7
CE CL A CL B EN
1 0 0 Qn-1(Note 2)
1011
1100
1111
0XX0
N2 N1 N0 EN 01234567
000110000000
001101000000
010100100000
011100010000
100100001000
101100000100
110100000010
111100000001
X X X 0 00000000
NOTES:
1. 1 = High level, 0 = Low level, X = Don’t care.
2. Qn-1 = Enable remains in previous state.
4-41
Static Electrical Specifications
PARAMETER SYMBOL
CDP1853/3, CDP1853C/3
CONDITIONS LIMITS
-55oC, +25oC +125oC
V
(V)
O
V
(V)
IN
V
DD
(V)
MIN MAX MIN MAX
UNITS
Quiescent Device
Current
(Note 1)
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
(Note 2)
Output Voltage
High-Level
(Note 2)
Input Low Voltage V
Input High Voltage V
Input Leakage Low I
V
V
I
I
I
OH
SS
OL
OL
OH
IL
- 0, 5 5 -50 - -100 - µA
- 0, 10 10 -500 - -1000 - µA
0.4 - 5 2.3 - 1.6 - mA
0.5 - 10 3.7 - 2.6 - mA
4.6 - 5 - -1.7 - -1.2 mA
9.5 - 10 - -3.7 - -2.6 mA
- 0, 5 5 - 0.1 - 0.2 V
- 0, 10 10 - 0.1 - 0.2 V
- 0, 5 5 4.9 - 4.8 - V
- 0, 10 10 9.9 - 9.8 - V
IL
0.8, 4.2 - 5 - 1.5 - 1.5 V
1, 9 - 10 - 3 - 3 V
IH
0.8, 4.2 - 5 3.5 - 3.5 - V
1, 9 - 10 7 - 7 - V
- 0 5 -1 - -5 - µA
- 0 10 -1 - -5 - µA
Input Leakage High I
IH
-55-1-5µA
-1010- 1 - 5µA
Input Capacitance CIN (Note 2) ----10-10pF
Output Capacitance C
(Note 2) ----15-15pF
OUT
NOTES:
1. The CDP1853C meets all 5V static electrical characteristics of the CDP1853 except quiescent device current for which the limits are:
ISS = -500µA at -55oC and +25oC and ISS = -1000µA at +125oC.
2. Guaranteed but not tested.
Dynamic Electrical Specifications See Figure 2, C
= 100pF, tR, tF = 15ns
L
LIMITS
-55oC, +25oC +125oC
V
PARAMETER SYMBOL
Propagation Delay Time: t
EOH
DD
(V)
MIN MAX MIN MAX
UNITS
5 - 175 - 275 ns
Chip Enable (CE) to Output High 10 - 90 - 150 ns
4-42
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