Intersil Corporation CDP1802AC-3 Datasheet

3-30
March 1997
CDP1802AC/3
High-Reliability CMOS 8-Bit Microprocessor
Features
• For Use In Aerospace, Military, and Critical Industrial Equipment
• Minimum Instruction Fetch
(Maximum ClockFrequency of 3.6MHz) at V
DD
= 5V , T
A
= +25oC
• Operation Over the Full Military
Temperature Range. . . . . . . . . . . . . . . -55
o
C to +125oC
• Any Combination of Standard RAM and ROM Up to 65,536 Bytes
• 8–Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus
• 16 x 16 Matrix of Registers for Use as Multiple Pro­gram Counters, Data Pointers, or Data Registers
• On-Chip DMA, Interrupt, and Flag Inputs
• High Noise Immunity. . . . . . . . . . . . . . . . . . 30% of V
DD
Description
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central
-Processing Unit (CPU) is designed for use
as a general purpose computing or control element in a wide range of stored
-program systems or products.
The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facili­tate system design.
The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 Series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt
-driven, or direct memory-access modes.
The CDP1802AC/3 is functionally identical to its predeces­sor, the CDP1802. The “A” version includes some perfor­mance enhancements and can be used as a direct replacement in systems using the CDP1802.
This type is supplied in 40 lead dual
-in-line sidebrazed
ceramic packages (D suffix).
Pinout
CDP1802AC/3 (SBDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP. RANGE
(oC) 5V - 3.2MHz
PKG
NO.
SBDIP -55 to 125 CDP1802ACD3 D40.6
13
1 2 3 4 5 6 7 8
9 10 11 12
14 15 16 17 18 19 20
CLOCK
WAIT
CLEAR
Q SC1 SC0
MRD BUS 7 BUS 6 BUS 5 BUS 4 BUS 3 BUS 2 BUS 1 BUS 0
V
CC
N2 N1 N0
V
SS
28
40 39 38 37 36 35 34 33 32 31 30 29
27 26 25 24 23 22 21
V
DD
XTAL DMA IN DMA OUT INTERRUPT MWR TPA TPB MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 EF1 EF2 EF3 EF4
File Number 1441.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
[ /Title (CDP1 802AC /
3)
/
Sub-
j
ect (High­Reli­ability CMOS 8-Bit Micro­proces­sor) /
Autho r () /
Key­words (Inter­sil Corpo­ration, 8-bit micro­proces­sors, 8 bit micro­proces­sors, periph­erals) /
Cre­ator () /
DOCI NFO pdf­mark
3-31
CDP1852 INPUT PORT
DAT A
CS1
CS2
CDP1852 OUTPUT PORT
CLOCK
CS1
CS2
MA0–7
N0
MRD
MWR
N1 TPB DATA TPA
CDP1802
8–BIT CPU
MRD
MA0–4
MWR
CS
CDP1824
32 BYTE RAM
MA0–7
DAT A
CEO
TPA
MRD
8–BIT DATA BUS
ADDRESS BUS
CDP1833 1K–ROM
DATA
FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM
CDP1802AC/3
3-32
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)
SBDIP Package. . . . . . . . . . . . . . . . . . . . 55 15
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range. . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
Storage Temperature Range (T
STG
). . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ±0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions T
A
= Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges
PARAMETER MIN MAX UNITS
DC Operating Voltage Range 4 6.5 V
Input Voltage Range V
SS
V
DD
V
Maximum Clock Input Rise or Fall Time - 1 µs
Performance Specifications
PARAMETER VDD (V) -55oC TO +25oC +125oC UNITS
Minimum Instruction Time (Note 1) 5 4.5 5.9 µs
Maximum DMA Transfer Rate 5 450 340 Kbytes/s
Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF, f
CL
5 DC-3.6 DC-2.7 MHz
NOTE:
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations.
Static Electrical Specifications All Limits are 100% Tested
PARAMETER
CONDITIONS -55oC, +25oC +125oC
UNITS
V
OUT
(V) V
IN,
(V) V
CC,VDD
(V) MIN MAX MIN MAX
Quiescent Device Current, I
DD
- - 5 - 100 - 250 µA
Output Low Drive (Sink) Current
(Except XTAL), I
OL
0.4 0, 5 5 1.20 - 0.90 - mA
XTAL 0.4 5 5 185 - 140 - µA
Output High Drive (Source) Current (Except XTAL), I
OH
4.6 0, 5 5 - -0.30 - -0.20 mA
XTAL 4.6 0 5 - -135 - -100 µA
Output Voltage Low-Level, V
OL
- 0, 5 5 - 0.1 - 0.2 V
Output Voltage High-Level, V
OH
- 0, 5 5 4.9 - 4.8 - V
CDP1802AC/3
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