Intersil Corporation CDP1802BC, CDP1802AC, CDP1802A Datasheet

CDP1802A, CDP1802A C,

/
j

/

/

/

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CDP1802BC

[ /Title
(CDP1
802A,
CDP18
02AC,
CDP18
02BC)

Sub-

ect
(CMO
S 8­Bit
Micro­proces­sors)

Autho
r ()

Key­words
(Inter­sil
Corpo­ration,
8-bit
micro­proces­sors, 8
bit
micro­proces­sors,
periph­erals)

Cre­ator ()

DOCI
NFO
pdf­mark

March 1997

Features

• Maximum Input Clock Maximum Frequency Options
At V

= 5V

DD

- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . .3.2MHz

- CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0MHz

• Maximum Input Clock Maximum Frequency Options
At V

= 10V

DD

- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . .6.4MHz

• Minimum Instruction Fetch
At V

= 5V

DD

- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs

- CDP1802BC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs

• Any Combination of Standard RAM and ROM Up to
65,536 Bytes

-Bit Parallel Organization With Bidirectional Data Bus

•8
and Multiplexed Address Bus

• 16 x 16 Matrix of Registers for Use as Multiple
Program Counters, Data Pointers, or Data Registers

•On

-Chip DMA, Interrupt, and Flag Inputs

• Programmable Single

• 91 Easy

-to-Use Instructions

-Execute Times

-Bit Output Port

Ordering Information

PART NUMBER

CDP1802ACE CDP1802BCE -40oC to +85oC PDIP E40.6
CDP1802ACEX CDP1802BCEX Burn-In E40.6
CDP1802ACQ CDP1802BCQ -40oC to +85oC PLCC N44.65
CDP1802ACD - -40oC to +85oC SBDIP D40.6
CDP1802ACDX CDP1802BCDX Burn-In D40.6

CMOS 8-Bit Microprocessors

Description

The CDP1802 family of CMOS microprocessors are 8-bit
register oriented central processing units (CPUs) designed
for use as general purpose computing or control elements in
a wide range of stored program systems or products.

The CDP1802 types include all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili­tate system design.

The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchro­nous interface to memories and external controllers for I/O
devices, and minimizes the cost of interface controllers. Fur­ther, the I/O interface is capable of supporting devices oper­ating in polled, interrupt driven, or direct memory access
modes.

The CDP1802A and CDP1802AC have a maximum input
clock frequency of 3.2MHz at V
CDP1802AC are functionally identical. They differ in that the
CDP1802A has a recommended operating voltage range of
4V to 10.5V, and the CDP1802AC a recommended operat­ing voltage range of 4V to 6.5V.

The CDP1802BC is a higher speed version of the
CDP1802AC, having a maximum input clock frequency of

5.0MHz at V
range of 4V to 6.5V.

TEMPERATURE RANGE PACKAGE PKG. NO.5V - 3.2MHz 5V - 5MHz

= 5V, and a recommended operating voltage

DD

= 5V. The CDP1802A and

DD

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

3-3

File Number

1305.2

Pinouts

CDP1802A, CDP1802AC, CDP1802BC

40 LEAD PDIP (PACKAGE SUFFIX E)

40 LEAD SBDIP (PACKAGE SUFFIX D)

TOP VIEW

44 LEAD PLCC

(PACKAGE TYPE Q)

TOP VIEW

CLOCK

WAIT

CLEAR

SC1
SC0

MRD
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0

V

CC

N2
N1
N0

V

SS

1
2
3

Q

4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40

V
XTAL

39

DMA IN

38

DMA OUT

37

INTERRUPT

36

MWR

35

TPA

34

TPB

33

MA7

32

MA6

31

MA5

30

MA4

29

MA3

28

MA2

27

MA1

26

MA0

25
24

EF1

23

EF2

22

EF3

21

EF4

DD

SC0

MRD
BUS 7
BUS 6
BUS 5

NC
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0

SC1QCLEAR

7
8
9
10
11
12
13
14
15
16
17

CC

V

WAIT

N2N1N0

DD

CLOCKNCV

44 43 42 41 40

123456

SS

NC

V

EF4

XTAL

262524232221201918

EF3

DMA-IN

DMA-OUT

2827

EF2

EF1

INTERRUPT

39
38
37
36
35
34
33
32
31
30
29

MA0

MWR
TPA
TPB
MA7
MA6
NC
MA5
MA4
MA3
MA2
MA1

CDP1852

INPUT PORT

DAT A

CDP1852

OUTPUT

PORT

ADDRESS BUS

CS2

CS1

CS1

CS2

CLOCK

N0

MRD

CDP1802

-BIT CPU

8

N1
TPB

MA0-7

DAT A

MWR

TPA

MRD

CDP1833

1K

TPA

FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM

MA0-7

-ROM

DAT A

CEO

MA0-4

MRD

CDP1824

32 BYTE RAM

MWR
CS

3-4

Block Diagram

CDP1802A, CDP1802AC, CDP1802BC

I/O REQUESTS

MEMORY ADDRESS LINES I/O FLAGS

EF1 EF3

MA0MA2MA4MA6

REGISTER
ARRAY
R

LATCH

AND

DECODE

EF2 EF4

CLOCK

CONTROL AND

LOGIC

TIMING LOGIC

MA7 MA5 MA3 MA1

MUX

A

INCR/
DECR

R(0).1 R(0).0

R(1).0R(1).1

R(2).1 R(2).0

R(9).1

R(9).0

R(A).0R(A).1

R(E).1

R(E).0

R(F).1 R(F).0

B

ALU

DF

D

8-BIT BIDIRECTIONAL DATA BUS

DMA
OUT

DMA

IN INT

TO INSTRUCTION

XTPIN

CONTROL

CLEAR

DECODE

WAIT

CLOCK
XTAL

SCO
SCI
Q LOGIC
TPA
TPB
MWR
MRD

STATE
CODES

SYSTEM
TIMING

N0
N1
N2

BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7

I/O
COMMANDS

FIGURE 2.

3-5

CDP1802A, CDP1802AC, CDP1802BC

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, (VDD)

(All Voltages Referenced to VSS Terminal)

CDP1802A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +11V

CDP1802AC, CDP1802BC. . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)

PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 50 N/A

PLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 46 N/A

SBDIP . . . . . . . . . . . . . . . . . . . . . . . . . 55 15

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW

Operating Temperature Range (TA)

Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Package Type E and Q. . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Storage Temperature Range (T

) . . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)

from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Lead Tips Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300oC

Recommended Operating Conditions T

= -40oC to +85oC. For maximum reliability, operating conditions should be selected so

A

that operation is always within the f ollo wing r anges:

TEST CONDITIONS CDP1802A CDP1802AC CDP1802BC

(NOTE 2)

PARAMETER

V

CC

(V)

V

DD

(V) MIN MAX MIN MAX MIN MAX

UNITS

DC Operating Voltage Range - - 4 10.5 4 6.5 4 6.5 V
Input Voltage Range - - V
Maximum Clock Input Rise or

4 to 6.5 4 to 6.5 - - - 1 - 1 µs

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

Fall Time

4 to 10.5 4 to 10.5 - 1 ---- µs

Minimum Instruction Time

5 5 5-5-3.2- µs

(Note 3)

5 10 4----- µs

10 102.5----- µs

Maximum DMA Transfer Rate 5 5 - 400 - 400 - 667 KBytes/s

5 10 -500----

10 10 -800----

Maximum Clock Input Frequency,

5 5 DC 3.2 DC 3.2 DC 5 MHz
fCL, Load Capacitance
(CL) = 50pF

5 10DC4----MHz

10 10DC6.4----MHz

NOTES:

1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.

2. VCC must never exceed VDD.

3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3

machine cycles - one Fetch and two Execute operations.

4. θJA is measured with component mounted on an evaluation board in free air.

3-6

CDP1802A, CDP1802AC, CDP1802BC

Static Electrical Specifications at T

= -40oC to +85oC, Except as Noted

A

CDP1802AC,

TEST CONDITIONS CDP1802A

CDP1802BC

VCC,

PARAMETER SYMBOL

Quiescent Device Current I

DD

V

OUT

(V)

V
(V)

V

IN

DD

(V) MIN

(NOTE 1)

TYP MAX MIN

(NOTE 1)

TYP MAX

UNITS

- - 5 - 0.1 50 - 1 200 µA

- - 10 - 1 200 - - - µA

Output Low Drive (Sink)

Current I

OL

0.4 0, 5 5 1.1 2.2 - 1.1 2.2 - mA
(Except XTAL) 0.5 0, 10 10 2.2 4.4 - - - - mA
XTAL 0.4 5 5 170 350 - 170 350 - µA

Output High Drive (Source)

Current I

OH

4.6 0, 5 5 -0.27 -0.55 - -0.27 -0.55 - mA
(Except XTAL) 9.5 0, 10 10 -0.55 -1.1 - - - - mA
XTAL 4.6 0 5 -125 -250 - -125 -250 - µA

Output Voltage - 0, 5 5 - 0 0.1 - 0 0.1 V

Low Level V

OL

- 0, 10 10 - 0 0.1 - - - V

Output Voltage - 0, 5 5 4.9 5 - 4.9 5 - V

High Level V

Input Low Voltage V

OH

IL

- 0, 10 10 9.9 10 - - - - V

0.5, 4.5 - 5 - - 1.5 - - 1.5 V

0.5, 4.5 - 5, 10 - - 1 - - - V
1, 9 - 10 - - 3 - - - V

Input High Voltage V

0.5, 4.5 - 5 3.5 - - 3.5 - - V

IH

0.5, 4.5 - 5, 10 4 - - - - - V
1, 9 - 10 7 - - - - - V

CLEAR Input Voltage V

H

- - 5 0.4 0.5 - 0.4 0.5 - V

Schmitt Hysteresis - - 5, 10 0.3 0.4 - - - - V

- - 10 1.5 2 - - - - V

Input Leakage Current I

IN

Any

0, 5 5 - ±10

Input

0, 10 10 - ±10

Three-State Output Leakage I

OUT

0, 5 0, 5 5 - ±10

Current 0, 10 0, 10 10 - ±10

-4

±1-±10

-4

±1- - -µA

-4

±1-±10

-4

±1- - -µA

-4

-4

±1 µA

±1 µA

Operating Current

CDP1802A, AC
at f = 3.2MHz

CDP1802BC

I

DDI

(Note 2)

--5-24-24mA

--5----36mA

at f = 5.0MHz

Minimum Data Retention

V

DR

VDD = V

DR

- 2 2.4 - 2 2.4 V

Voltage
Data Retention Current I

DR

VDD = 2.4V - 0.05 - - 0.5 - µA

3-7

CDP1802A, CDP1802AC, CDP1802BC

Static Electrical Specifications at T

= -40oC to +85oC, Except as Noted (Continued)

A

TEST CONDITIONS CDP1802A

V

PARAMETER SYMBOL

Input Capacitance C
Output Capacitance C

IN

OUT

OUT

(V)

NOTES:

1. Typical values are for TA = +25oC and nominal VDD.

2. Idle “00” at M(0000), CL = 50pF.

Dynamic Electrical Specifications T

= -40oC to +85oC, CL = 50pF, VDD±5%, Except as Noted

A

PARAMETER SYMBOL

PROPAGATION DELAY TIMES

Clock to TPA, TPB t

PLH

, t

PHL

CDP1802AC,

CDP1802BC

VCC,
V
(V)

V

IN

DD

(V) MIN

(NOTE 1)

TYP MAX MIN

(NOTE 1)

TYP MAX

- 5 7.5 - 5 7.5 pF

- 10 15 - 10 15 pF

TEST

CONDITIONS

CDP1802A,

CDP1802AC CDP1802BC

(NOTE 1)

TYP MAX

(NOTE 1)

TYP MAX

5 5 200 300 200 300 ns
5 10 150 250 - - ns

UNITS

UNITSVCC (V) VDD (V)

Clock-to-Memory High-Address Byte t

Clock-to-Memory Low-Address Byte Valid t

PLH

PLH

Clock to MRD t

Clock to MRD t

Clock to MWR t

Clock to (CPU DATA to BUS) Valid t

PLH

PLH

, t

, t

PHL

PLH

, t

, t

PHL

PHL

PHL

PHL

10 10 100 150 - - ns

5 5 600 850 475 525 ns
5 10 400 600 - - ns

10 10 300 400 - - ns

5 5 250 350 175 250 ns
5 10 150 250 - - ns

10 10 100 150 - - ns

5 5 200 300 175 275 ns
5 10 150 250 - - ns

10 10 100 150 - - ns

5 5 200 350 175 275 ns
5 10 150 290 - - ns

10 10 100 175 - - ns

5 5 200 300 175 225 ns
5 10 150 250 - - ns

10 10 100 150 - - ns

5 5 300 450 250 375 ns
5 10 250 350 - - ns

10 10 100 200 - - ns

3-8

CDP1802A, CDP1802AC, CDP1802BC

Dynamic Electrical Specifications T

PARAMETER SYMBOL

Clock to State Code t

Clock to Q t

Clock to N (0 - 2) t

MINIMUM SET UP AND HOLD TIMES

Data Bus Input Set Up t

= -40oC to +85oC, CL = 50pF, VDD±5%, Except as Noted (Continued)

A

PLH

TEST

CONDITIONS

, t

PHL

5 5 300 450 250 400 ns

CDP1802A,

CDP1802AC CDP1802BC

(NOTE 1)

TYP MAX

(NOTE 1)

TYP MAX

5 10 250 350 - - ns

10 10 150 250 - - ns

PLH

, t

PHL

5 5 250 400 200 300 ns
5 10 150 250 - - ns

10 10 100 150 - - ns

PLH

, t

PHL

5 5 300 550 275 350 ns
5 10 200 350 - - ns

10 10 150 250 - - ns

SU

5 5 -20 25 -20 0 ns
5 10 0 50 - - ns

UNITSVCC (V) VDD (V)

Data Bus Input Hold t

(Note 2)

DMA Set Up t

DMA Hold t

(Note 2)

Interrupt Set Up t

Interrupt Hold t

(Note 2)

WAIT Set Up t

SU

SU

SU

10 10 -10 40 - - ns

H

5 5 150 200 125 150 ns
5 10 100 125 - - ns

10 10 75 100 - - ns

5 5 0 30 0 30 ns
5 10 0 20 - - ns

10 10 0 10 - - ns

H

5 5 150 250 100 150 ns
5 10 100 200 - - ns

10 10 75 125 - - ns

5 5 -75 0 -75 0 ns
5 10 -50 0 - - ns

10 10 -25 0 - - ns

H

5 5 100 150 75 125 ns
5 10 75 100 - - ns

10 10 50 75 - - ns

5 5 10 50 20 40 ns
5 10 -10 15 - - ns

10 10 0 25 - - ns

3-9

CDP1802A, CDP1802AC, CDP1802BC

Dynamic Electrical Specifications T

PARAMETER SYMBOL

EF1-4 Set Up t

EF1-4 Hold t

Minimum Pulse Width Times

CLEAR Pulse Width t

CLOCK Pulse Width t

= -40oC to +85oC, CL = 50pF, VDD±5%, Except as Noted (Continued)

A

SU

TEST

CONDITIONS

5 5 -30 20 -30 0 ns

CDP1802A,

CDP1802AC CDP1802BC

(NOTE 1)

TYP MAX

(NOTE 1)

TYP MAX

5 10 -20 30 - - ns

10 10 -10 40 - - ns

H

5 5 150 200 100 150 ns

(Note 2)

5 10 100 150 - - ns

10 10 75 100 - - ns

WL

5 5 150 300 100 150 ns

(Note 2)

5 10 100 200 - - ns

10 10 75 150 - - ns

WL

5 5 125 150 90 100 ns
5 10 100 125 - - ns

10 10 60 75 - - ns

UNITSVCC (V) VDD (V)

NOTES:

1. Typical values are for TA = +25oC and nominal VDD.

2. Maximum limits of minimum characteristics are the values above which all devices function.

Timing Specifications as a function of T(T = 1/f

) at TA = -40 to +85oC, Except as Noted

CLOCK

CDP1802A,

TEST CONDITIONS

CDP1802AC CDP1802BC

(NOTE 1)

PARAMETERS SYMBOL

High-Order Memory-Address Byte

t

SU

5 5 2T-550 2T-400 2T-325 2T-275 ns

Set Up to TPA Time

5 10 2T-350 2T250 - - ns

10 10 2T-250 2T-200 - - ns

High-Order Memory-Address Byte

t

H

5 5 t/2-25 T/2-15 T/2-25 T/2-15 ns

Hold After TPA Time

5 10 T/2-35 T/2-25 - - ns

10 10 T/2-10 T/2-+0 - - ns

Low-Order Memory-Address Byte

t

H

5 5 T-30 T+0 T-30 T+0 ns

Hold After WR Time

5 10 T-20 T+0 - - ns

10 10 T-10 T+0 - - ns

CPU Data to Bus Hold After WR

t

H

5 5 T-200 T-150 T-175 T-125 ns

Time

5 10 T-150 T-100 - - ns

TYP MIN

(NOTE 1)

TYP

UNITSVCC (V) VDD (V) MIN

10 10 T-100 T-50 - - ns

3-10

CDP1802A, CDP1802AC, CDP1802BC

Timing Specifications as a function of T(T = 1/f

TEST CONDITIONS

PARAMETERS SYMBOL

Required Memory Access Time

t

ACC

Address to Data

MRD to TPA t

SU

NOTE:

1. Typical values are for TA = +25oC and nominal VDD.

Timing Waveforms

FETCH (READ) EXECUTE (WRITE)

CLOCK

00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00

) at TA = -40 to +85oC, Except as Noted

CLOCK

CDP1802A,

CDP1802AC CDP1802BC

(NOTE 1)

TYP MIN

(NOTE 1)

TYP

UNITSVCC (V) VDD (V) MIN

5 5 5T-375 5T-250 5T-225 5T-175 ns
5 10 5T-250 5T-150 - - ns

10 10 5T-190 5T-100 - - ns

5 5 T/2-25 T/2-18 T/2-20 T/2-15 ns
5 10 T/2-20 T/2-15 - - ns

10 10 T/2-15 T/2-10 - - ns

ADDRESS

TPA

TPB

MRD

MWR

DATA VALID INPUT DATA

FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE

HI BYTE LOW BYTEHI BYTE LOW BYTE

VALID OUTPUT DATA

3-11