Intersil Corporation CD54ACT299F3A, CD54AC299F3A Datasheet

Specifications CD54AC299/3A, CD54ACT299/3A

Absolute Maximum Ratings

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current, Per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or GND Current, ICC or I

GND

For Up to 4 Outputs Per Device, Add ±25mA For Each

Additional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Recommended Operating Conditions

Supply Voltage Range, V

Unless Otherwise Specified, All Voltages Referenced to GND
TA = Full Package Temperature Range

CD54AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

CD54ACT Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO. . . . . . . . . . . . . . . . . . 0V to V

CC

Power Dissipation Per Package, P

D

TA = -55oC to +100oC (Package F) . . . . . . . . . . . . . . . . . . 500mW

TA = +100oC to +125oC (Package F) . . . . . . . . Derate Linearly at

8mW/oC to 300mW

Operating Temperature Range, T

A

Package Type F. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Storage Temperature, T

. . . . . . . . . . . . . . . . . .-65oC to +150oC

STG

Lead Temperature (During Soldering)

At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm)

From Case For 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm)

With Solder Contacting Lead Tips Only. . . . . . . . . . . . . . . +300oC

Operating Temperature, TA . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Input Rise and Fall Slew Rate, dt/dv

at 1.5V to 3V (AC Types). . . . . . . . . . . . . . . . . . . 0ns/V to 50ns/V

at 3.6V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 20ns/V

at 4.5V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 10ns/V

CC

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SEMICONDUCTOR

CD54AC299/3A

CD54ACT299/3A

COMPLETE DATA SHEET

June 1997

Description

The CD54AC299/3A and CD54ACT299/3A are three-state,
8-input universal shift/storage registers with common parallel
I/O pins. These devices utilize the Harris Advanced CMOS
Logic technology. These registers have four synchronous
operating modes controlled by the two select inputs as shown
in the Mode Select (S0, S1) table. The Mode Select, the Serial
Data (DS0, DS7), and the Parallel Data (I/O
only to the LOW-to-HIGH transition of the clock pulse (CP).
S0, S1 and Data inputs must be present one setup time prior
to the positive transition of the clock.

The Master Reset (
input. When
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (QO) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is accom­plished by tying the Q7 of the last stage to the DS0 of the
first stage.

The three-state input/output (I/O) port has three modes of
operation

MR is LOW, the register is cleared regardless of

COMING SOON!

- I/O7) respond

0

MR) is an asynchronous active-LOW

8-Input Universal Shift/Storage Registers

with Common Parallel I/O Pins

2. When both S0 and S1 are HIGH, I/O terminals are in the
high-impedance state but being input ports, ready for par­allel data to be loaded into eight registers with one clock
transition regardless of the status of

3. Either one of the two Output Enable inputs being HIGH
will force I/O terminals to be in the off state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.

The CD54AC299/3A and CD54ACT299/3A are supplied in
20 lead dual-in-line ceramic packages (F suffix).

ACT INPUT LOAD TABLE

INPUT UNIT LOAD (NOTE 1)

S1, S2, OE1, OE2 0.83

SL, CP 0.67

MR 1.33

NOTE:

1. Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA Max at +25oC.

OE1 and OE2.

1. Both Output Enable (

OE1 and OE2) inputs are LOW and
S0 or S1 or both are LOW, the data in the register is
present at the eight outputs.

Functional Diagram

7

I/O

BUS LINE

OUTPUTS

STANDARD OUTPUT

I/O
I/O
I/O

Q0

S0

0

6

2

5

4

4

6

8

1

I/O

THREE-STATE

OUTPUTS

GND DS0 DS7

12 2 3 9

THREE-STATE

CONTROL

SHIFT

REGISTER

MODE

SELECTION

181110

MROE2OE1CP

THREE-STATE

OUTPUTS

I/O

20

V

CC

13

I/O

1

14

I/O

3

BUS LINE

15
16

17

19

OUTPUTS

I/O

5

I/O

7

Q7

STANDARD OUTPUT

S1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright

© Harris Corporation 1994

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File Number 3907