• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25
o
C
Applications
• Driving Common Cathode LED Displays
• Multiplexing with Common Cathode LED Displays
• Driving Incandescent Displays
• Driving Low Voltage Fluorescent Displays
Description
CD4511BMS is a BCD-to-7-Segment latch decoder drivers
constructed with CMOS logic and n-p-n bipolar transistor
output devices on a single monolithic structure. These
devices combine the low quiescent power dissipation and
high noise immunity features of Intersil CMOS with n-p-n
bipolar output transistors capable of sourcing up to 25mA.
This capability allows the CD4511BMS types to drive LED’s
and other displays directly.
Lamp Test (
inputs are provided to test the display, shut off or intensity
modulate it, and store or strobe a BCD code, respectively.
Several different signals may be multiplexed and displayed
when external multiplexing circuitry is used.
LT), Blanking (BL), and Latch Enable or Strobe
Pinout
CD4511BMS
TOP VIEW
1
B
2
C
3
LT
4
BL
VSS
5
D
6
A
7
8
/STROBE
LE
Functional Diagram
LT
7
A
1
B
BCD
INPUTS
C
D
LE/STROBE
VSS = 8
VDD = 16
L
A
T
C
2
H
6
5
BL
VDD
16
f
15
14
g
13
a
12
b
11
c
d
10
e
9
3
13
a
12
D
E
C
O
D
E
R
4
D
R
I
V
E
R
b
11
c
7
10
SEGMENT
d
OUTPUTS
9
e
15
f
14
g
These devices are similar to the type MC14511.
The CD4511BMS is supplied in these 16-lead outline
packages:
7-Segment Display
Braze Seal DIPH4W
Frit Seal DIPH2R
Ceramic FlatpackH6W
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
Supply CurrentIDDVDD = 20V, VIN = VDD or GND1, 4+25oC-25µA
N Threshold VoltageVNTHVDD = 10V, ISS = -10µA1, 4+25oC-2.8-0.2V
N Threshold Voltage
∆VTNVDD = 10V, ISS = -10µA1, 4+25oC-±1V
Delta
P Threshold VoltageVTPVSS = 0V, IDD = 10µA1, 4+25oC0.22.8V
P Threshold Voltage
∆VTPVSS = 0V, IDD = 10µA1, 4+25oC-±1V
Delta
FunctionalFVDD = 18V, VIN = VDD or GND1+25oCVOH >
VDD/2
Propagation Delay TimeTPHL
VDD = 3V, VIN = VDD or GND
VDD = 5V1, 2, 3, 4+25oC-1.35 x
TPLH
VOL <
VDD/2
+25oC
Limit
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit.
4. Read and Record
UNITSMINMAX
UNITSMINMAX
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETERSYMBOLDELTA LIMIT
Supply Current - MSI-2IDD± 1.0µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading
Output Current (Source)IOH5A± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
METHODGROUP A SUBGROUPSREAD AND RECORD
Initial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
7-1173
Specifications CD4511BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
CONFORMANCE GROUP
PDA (Note 1)100% 50041, 7, 9, Deltas
Interim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1178
CD4511BMS
Applications
MULTIPLEXING SCHEME SHOWING
2 OF 7 SEGMENTS CONNECTED
TRANSISTORS T1 - T4 (2N3053 OR 2N2102)
HAVE IC MAX. RATING > 7 x ISEG
DUTY CYCLE = 25%
ISEG = (IDIODEAVG) x 4
(VOH - VDF-VCE)
R =
ISEG
Interfacing with Various Displays (Continued)
CD4511BMS
Q0
Q1
Q2
Q3
VDD
a
b
c
d
e
f
g
+
-
R
R
VOH
5
6
7
1
CD4024BMS
2
VO1
V02
VO3
LT
A
B
C
D
LE
VDD
BL
24
12
311
CD4555BMS
1
9
VSS
VSS
ISEG
+
VDF
-
T1
VSS
+
VCE
T2
VSS
T3
VSS
T4
VSS
FIGURE 12. MULTIPLEXING WITH COMMON CATHODE 7-SEGMENT LED DISPLAYS (EXAMPLE HEWLET-PACKARD 5082-7404
4 CHARACTER DISPLAY OR 4 DISCRETE MONOSANTO MAN 3 DISPLAYS)
Waveforms
20ns
20ns
10%
50%
90%
50%
10%
20ns
10%
tSU
90%
tW
50%
90%
VDD
tHOLD
50%
20ns
VDD
0
VDD
0
FOR SETUP
FOR HOLD
0
OUTPUT
tr, tf = 20ns
DATA
INPUT
tPHL
trtf
VDD
90%
50%
10%
tTLHtTHL
90%
50%
10%
tPLH
0
VDD
0
LE
DATA
INPUTS
OUTPUT
STROBE
tr, tf = 20ns
FIGURE 13. DYNAMIC WAVEFORMS
Chip Dimensions and Pad Layout
7-1179
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10
-3
inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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