Intersil Corporation CD4096BMSFN3331, CD4095BMS Datasheet

7-1094

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4095BMS
CD4096BMS

CMOS Gated J-K

Master-Slave Flip-Flops

Features

• Set-Reset Capability

• High Voltage Types (20V Rating)

• CD4095BMS Non-Inverting J and K Inputs

• CD4096BMS Inverting and Non-Inverting J and K
Inputs

• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V

• Gated Inputs

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1µA at 18V Over Full Pack­age Temperature Range; 100nA at 18V and +25

o

C

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets all requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

• Registers

• Counters

• Control Circuits

Description

CD4095BMS and CD4096BMS are J-K Master-Slave Flip­Flops featuring separate AND gating of multiple J and K
inputs. The gated J-K inputs control transfer of information
into the master section during clocked operation. Information
on the J-K inputs is transferred to the Q and

Q outputs on
the positive edge of the clock pulse. SET and RESET inputs
(active high) are provided for asynchronous operation.

The CD4095BMS and CD4096BMS are supplied in these 14
lead outline packages:

Braze Seal DIP H4Q
Frit Seal DIP H1A

File Number

3331

Pinouts

CD4095BMS

TOP VIEW

CD4096BMS

TOP VIEW

Functional Diagrams

CD4095BMS

CD4096BMS

NC

RESET

J1
J2
J3

Q

VSS

VDD
SET
CLOCK
K1
K2
K3
Q

1
2
3
4
5
6
7

14
13
12
11
10

9
8

NC

RESET

J1
J2
J3

Q

VSS

VDD
SET
CLOCK
K1
K2
K3
Q

1
2
3
4
5
6
7

14
13
12
11
10

9
8

NC = NO CONNECTION

VDD = 14
VSS = 7

SET

J2
J3

13

3

5

4

J1

K2
K3

11

9

10

K1

12

CLOCK

S

JQ

CL

K

R

QQQ

RESET

2

NC = 1

6

8

VDD = 14
VSS = 7

SET

J2
J3

13

3

5

4

J1

K2
K3

11

9

10

K1

12

CLOCK

S

JQ

CL

K

R

QQQ

RESET

2

NC = 1

6

8

December 1992

7-1095

Specifications CD4095BMS, CD4096BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

o

C to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG) . . . . . . . . . . . -65

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

o

C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θ

ja

θ

jc

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

o

C/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55

o

C to +100oC (Package Type D, F, K). . . . . . 500mW

For TA = +100

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

o

C-2µA

2 +125oC - 200 µA

VDD = 18V, VIN = VDD or GND 3 -55oC-2µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

o

C -100 - nA

2 +125oC -1000 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

2 +125oC - 1000 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD/2

VOL <
VDD/2

V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

Input Voltage High
(Note 2)

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

Input Voltage Low
(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3 +25oC, +125oC, -55oC- 4 V

Input Voltage High
(Note 2)

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

1, 2, 3 +25oC, +125oC, -55oC11 - V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

7-1096

Specifications CD4095BMS, CD4096BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Propagation Delay
Clock to Output

TPHL1
TPLH1

VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

10, 11 +125oC, -55oC - 675 ns

Propagation Delay
Set or Reset to Output

TPHL2
TPLH2

VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns

10, 11 +125oC, -55oC - 405 ns

Transition Time TTHL

TTLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Maximum Clock Input
Frequency

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3.5 - MHz

10, 11 +125oC, -55oC 2.59 - MHz

NOTES:

1. VDD = 5V, CL = 50pF, RL = 200K

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

+125oC-30µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC-60µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC - 120 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

-50mV

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

-50mV

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

4.95 - V

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

9.95 - V

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA