Intersil Corporation CD4075BMS, CD4071BMS Datasheet

CD4071BMS, CD4072BMS

CD4075BMS

December 1992

Features

• High-Voltage Types (20V Rating)

• CD4071BMS Quad 2-Input OR Gate

• CD4072BMS Dual 4-Input OR Gate

• CD4075BMS Triple 3-Input OR Gate

• Medium Speed Operation:

- tPHL, tPLH = 60ns (typ) at 10V

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25oC

• Standardized Symmetrical Output Characteristics

• Noise Margin (Over Full Package T emperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Description

CD4071BMS, CD4072BMS and CD4075BMS OR gates pro­vide the system designer with direct implementation of the
positive-logic OR function and supplement the existing fam­ily of CMOS gates.

Pinout

J = A + B + C + D

J = A + B

K = C + C

VSS

NC

VSS

CD4071BMS

TOP VIEW

A

1
2

B

3
4

C

5
6

D

7

CD4072BMS

TOP VIEW

1
2

A

3

B

4

C

5

D

6
7

NC = NO CONNECTION

CMOS OR Gate

14

VDD

13

H

12

G

11

M = G + H

10

L = E + F

9

F

8

E

VDD

14
13

K = E +F + G + H

12

H

11

G

10

F

9

E

8

NC

The CD4071BMS, CD4072BMS and CD4075BMS are supplied
in these 14 lead outline packages:

Braze Seal DIP *H4H †H4Q
Frit Seal DIP H1B
Ceramic Flatpack H3W
*CD4071, CD4072 †CD4075 Only

K = D + E + F

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-444

A
B
D
E

VSS

1
2
3
4
5

F

6
7

CD4075BMS

TOP VIEW

14

VDD

13

G

12

H

11

I

10

L = G + H + I

9

J = A + B + C

8

C

File Number

3323

Functional Diagram

CD4071BMS, CD4072BMS, CD4075BMS

VDD

14

B
A

D
C

F
E

12

H

13

G

A
B

C
D

E

10

F

11

G

12

H

1
2

5
6

8
9

VSS

CD4071BMS

VDD

2
3

4
5

9

3

J

4

K

10

L

11

M

7

14

1

J

13

K

C
B

A
F

E
D

11

I

12

H

13

G

CD4072BMS

1
2
8

3
4
5

CD4075BMS

VSS

VDD

VSS

7

14

9

J

6

K

10

L

7

7-445

Specifications CD4071BMS, CD4072BMS, CD4075BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 0.5 µA

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55
For TA = +100

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

C to +100oC (Package Type D, F, K). . . . . . 500mW

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

ja

o

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

2 +125oC-50µA

o

C - 0.5 µA

o

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-446

Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTES 1, 2)

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Propagation Delay TPHL

TPLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 µA

VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 90 ns

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 338 ns

10, 11 +125oC, -55oC - 270 ns

+125oC - 7.5 µA

+125oC-15µA

+125oC-30µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -2.6 mA

-55oC - -4.2 mA

-55oC

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

7-V

7-447

Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Transition Time TTHL

TTLH

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 2.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

TPLH

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

LIMITS

VOL <
VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

3. See Table 2 for +25oC limit.

4. Read and Record

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

UNITSMIN MAX

V

ns

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - SSI IDD ±0.1µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

METHOD GROUP A SUBGROUPS READ AND RECORD

7-448

Specifications CD4071BMS, CD4072BMS, CD4075BMS

TABLE 6. APPLICABLE SUBGROUPS (Continued)

MIL-STD-883

CONFORMANCE GROUP

Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

FUNCTION OPEN GROUND VDD 9V ± -0.5V

PART NUMBER CD4071BMS
Static Burn-In 1

Note 1
Static Burn-In 2

Note 1
Dynamic Burn-

In Note 1
Irradiation

Note 2
PART NUMBER CD4072BMS
Static Burn-In 1

Note 1
Static Burn-In 2

Note 1
Dynamic Burn-

In Note 1
Irradiation

Note 2
PART NUMBER CD4075BMS
Static Burn-In 1

Note 1
Static Burn-In 2

Note 1
Dynamic Burn-

In Note 1
Irradiation

Note 2

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

3, 4, 10, 11 1, 2, 5 - 9, 12 - 13 14

3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,

- 7 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12,

3, 4, 10, 11 7 1, 2, 5, 6, 8, 9,

1, 6, 8, 13 2 - 5, 7, 9 - 12 14

1, 6, 8, 13 7 2 - 5, 9 - 12, 14

6, 8 7 14 1, 13 2 - 5, 9 - 12

1, 6, 8, 13 7 2 - 5, 9 - 12, 14

6, 9, 10 1 - 5, 7, 8, 11 - 13 14

6, 9, 10 7 1 - 5, 8, 11 - 14

- 7 14 6, 9, 10 1 - 5, 8, 11 - 13

6, 9, 10 7 1 - 5, 8, 11 - 14

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

12 - 14

12 - 14

TEST READ AND RECORD

OSCILLATOR

50kHz 25kHz

13

7-449

CD4071BMS, CD4072BMS, CD4075BMS

VDD

14

*

1 (6, 8, 13)

*

2 (5,9, 12)

2 (12)

p

p

n

p

n

VSS

p

n

n

7

pp

nn

3 (4, 10, 11)

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

B

1 (6, 8, 13)

2 (5, 9, 12)

A

FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

VDDVDD

**

INV.1

VDD

p

p

p

n

*

n

n

p

p

n

n

VDD

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

J

3 (4, 10, 11)

VDD

p

1 (13)

n

VSS

VSS

p

*

3 (11)

INV 2**

*

5 (9)

*

4 (10)

INVERTERS 2, 3 AND 4 ARE IDENTICAL TO INVERTER 1.

**

INV 3**

n

INV 4**

VSS

FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

A

2 (12)

B

3 (11)

D

5 (9)

C

4 (10)

FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

VSS

VDD
p

n

VSS

VSS

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

J

1 (13)

VDD

VSS

7-450

CD4071BMS, CD4072BMS, CD4075BMS

VDD

14

8 (5, 13)

2 (4, 12)

1 (3, 11)

pp

p

*

n

p

p

n

n

n

p

n

*

n

*

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

A

1 (3, 11)

B

2 (4, 12)

C

8 (5, 13)

p

n

7

VSS

n

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

p

9 (6, 10)

n

VDD

VSS

J

9 (6, 10)

FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

Typical Performance Characteristics

20

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 15V

15

10

5

OUTPUT VOLTAGE (VO) (V)

0

FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERIS-

10V

5V

5101520

INPUT VOLTAGE (VIN) (V)

TICS

200

AMBIENT TEMPERATURE (TA) = +25oC

150

SUPPLY VOLTAGE (VDD) = 5V

100

50

10V

15V

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

0

20 40 60 80

LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

7-451

CD4071BMS, CD4072BMS, CD4075BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

30

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

25

20

15

10V

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

5V

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10.0

7.5

10V

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

5V

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

SUPPLY VOLTAGE (VDD) = 5V

100

10V

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

15V

LOAD CAPACITANCE (CL) (pF)

FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

5

10

AMBIENT TEMPERATURE (TA) = +25oC

8
6

POWER DISSIPATION PER GATE (PD) (µW)

4
2

4

10

8
6

4
2

3

10

8
6

4
2

2

10

8
6

4
2

10

SUPPLY VOLTAGE (VDD) = 15V

10V

10V

5V

CL = 50pF
CL = 15pF

11010

864286422

2

INPUT FREQUENCY (fI) (kHz)

FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONAS A

FUNCTION OF FREQUENCY

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

2864

864

3

10

4

10

7-452

CD4071BMS, CD4072BMS, CD4075BMS

Chip Dimensions and Pad Layouts

CD4071BMS

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

CD4075BMS

Dimensions in parentheses are in millimeters and are

derived from the basic inch dimensions as indicated.

Grid graduations are in mils (10

-3

inch)

CD4072BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

453