• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Monostable Multivibrator Features
• Positive or Negative Edge Trigger
• Output Pulse Width Independent of Trigger Pulse
Duration
• Retriggerable Option for Pulse Width Expansion
• Internal Power-On Reset Circuit
• Long Pulse Widths Possible Using Small RC Components by Means of External Counter Provision
• Fast Recovery Time Essentially Independent of Pulse
Width
• Pulse-Width Accuracy Maintained at Duty Cycles
Approaching 100%
Astable Multivibrator Features
• Free-Running or Gatable Operating Modes
• 50% Duty Cycle
• Oscillator Output Available
• Good Astable Frequency Stability: Frequency Deviation:
o
-=±2% + 0.03%/
-=±0.5% + 0.015%/
C at 100kHz
o
C at 10kHz (Circuits “Trimmed”
to Frequency VDD = 10V ± 10%
Applications
Digital equipment where low power dissipation and/or high noise
immunity are primary design requirements
• Envelope Detection
• Frequency Multiplication
• Frequency Division
• Frequency Discriminators
• Timing Circuits
• Time Delay Applications
Description
CD4047BMS consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge triggered
monostable multivibrator action with retriggering and external counting
options.
Inputs include +TRIGGER, -TRIGGER, ASTABLE,
RETRIGGER, and EXTERNAL RESET . Buffered outputs are Q,
OSCILLAT OR. In all modes of operation, an external capacitor must be
connected between C-Timing and RC-Common terminals, and an
external resistor must be connected between the R-Timing and RCCommon terminals.
Astable operation is enabled by a high level on the ASTABLE input or a
low level on the ASTABLE input, or both. The period of the square wave
at the Q and
external components employed. “True” input pulses on the ASTABLE
input or “Complement” pulses on the
be used as a gatable multivibrator. The OSCILLA T OR output period will
be half of the Q terminal output in the astable mode. However, a 50%
duty cycle is not guaranteed at this output.
The CD4047BMS triggers in the monostable mode when a positive
going edge occurs on the +TRIGGER input while the -TRIGGER is held
low. Input pulses may be of any duration relative to the output pulse.
If retrigger capability is desired, the RETRIGGER input is pulsed. The
retriggerable mode of operation is limited to positive going edge. The
CD4047BMS will retrigger as long as the RETRIGGER input is high,
with or without transitions (See Figure 31)
An external countdown option can be implemented by coupling “Q” to
an external “N” counter and resetting the counter with trigger pulse. The
counter output pulse is fed back to the
tion equal to N times the period of the multivibrator.
A high level on the EXTERNAL RESET input assures no output pulse
during an “ON” power condition. This input can also be activated to terminate the output pulse at any time. For monostable operation, whenever VDD is applied, an internal power on reset circuit will clock the Q
output low within one output period (tM).
The CD4047BMS is supplied in these 14-lead outline packages:
Braze Seal DIPH4Q
Frit Seal DIPH1B
Ceramic Flatpack H3W
Pinout
Q Outputs in this mode of operation is a function of the
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
UNITSMINMAX
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
UNITSMINMAX
Supply CurrentIDDVDD = 20V, VIN = VDD or GND1, 4+25oC-7.5µA
N Threshold VoltageVNTHVDD = 10V, ISS = -10µA1, 4+25oC-2.8-0.2V
N Threshold Voltage
∆VTNVDD = 10V, ISS = -10µA1, 4+25oC-±1V
Delta
P Threshold VoltageVTPVSS = 0V, IDD = 10µA1, 4+25oC0.22.8V
P Threshold Voltage
∆VTPVSS = 0V, IDD = 10µA1, 4+25oC-±1V
Delta
FunctionalFVDD = 18V, VIN = VDD or GND1+25oCVOH >
VDD/2
Propagation Delay TimeTPHL
VDD = 3V, VIN = VDD or GND
VDD = 5V1, 2, 3, 4+25oC-1.35 x
TPLH
VOL <
VDD/2
ns
+25oC
Limit
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETERSYMBOLDELTA LIMIT
Supply Current - MSI-1IDD± 0.2µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading
Output Current (Source)IOH5A± 20% x Pre-Test Reading
V
7-901
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