Intersil Corporation CD4043BMS, CD4044BMS Datasheet

CD4043BMS CD4044BMS
December 1992
Features
• High Voltage Types (20V Rating)
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
o
- 100nA at 18V and 25
C
• Noise Margin (Over Full Package T emperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”
Applications
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
Pinout
CMOS Quad 3 State R/S Latches
CD4043BMS
TOP VIEW
1
Q4
2
Q1
3
R1
4
S1
ENABLE
ENABLE
5 6
S2
7
R2
8
VSS
NC = NO CONNECTION
CD4044BMS
TOP VIEW
1
Q4
2
NC
3
S1
4
R1
5 6
R2
7
S2
8
VSS
NC = NO CONNECTION
VDD
R4
S4
NC
S3
11
R3
Q3
9
Q2
VDD
S4
R4
Q1
R3
11
S3
Q3
9
Q2
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR latches and the CD4044BMS types are quad cross-coupled 3­state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are con­trolled by a common ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. A logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs, results in an open circuit feature allows common busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16­lead outline packages:
Braze Seal DIP *H4T †H4T Frit Seal DIP *H1C †HIE Ceramic Flatpack *H3X †H6W *CD4043B Only †CD4044B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-876
File Number
3311
Specifications CD4043BMS, CD4044BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +125oC
o
C to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA
VDD = 18V, VIN = VDD or GND 3 -55
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2) Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2) Input Voltage Low
(Note 2) Input Voltage High
(Note 2) Tri-State Output
Leakage
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
IOZL VIN = VDD or GND
VOUT = 0V
VDD = 20V 1 +25oC -0.4 - µA
VDD = 18V 3 -55oC -0.4 - µA Tri-State Output
Leakage
IOZH VIN = VDD or GND
VOUT = VDD
VDD = 20V 1 +25oC - 0.4 µA
VDD = 18V 3 -55oC - 0.4 µA NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
Thermal Resistance . . . . . . . . . . . . . . . . θ
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55 For TA = +100
o
C
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
C to +100oC (Package Type D, F, K). . . . . . 500mW
o
C to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
ja
o
C/W 20oC/W
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
GROUP A
LIMITS
SUBGROUPS TEMPERATURE
2 +125oC - 200 µA
o
C-2µA
o
C -100 - nA
2 +125oC -1000 - nA
2 +125oC - 1000 nA
VOL <
VDD/2
VDD/2
1, 2, 3 +25oC, +125oC, -55oC- 4 V
1, 2, 3 +25oC, +125oC, -55oC11 - V
2 +125oC -12 - µA
2 +125oC-12µA
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
θ
jc
UNITSMIN MAX
V
7-877
Specifications CD4043BMS, CD4044BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
PARAMETER SYMBOL CONDITIONS
Propagation Delay Set or Reset to Q
Propagation Delay 3 - State Enable to Q
Propagation Delay 3 - State Enable to Q
Transition Time TTHL
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
TPHL TPLH
TPHZ TPZH
TPLZ TPZL
TTLH
VDD = 5V, VIN = VDD or GND (Notes 1, 2)
VDD = 5V, VIN = VDD or GND (Notes 2, 3)
VDD = 5V, VIN = VDD or GND (Notes 2, 3)
VDD = 5V, VIN = VDD or GND (Notes 1, 2)
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA
SUBGROUPS TEMPERATURE
9 +25oC - 300 ns
10, 11 +125oC, -55oC - 405 ns
9 +25oC - 230 ns
10, 11 +125oC, -55oC - 311 ns
9 +25oC - 180 ns
10, 11 +125oC, -55oC - 243 ns
9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
+125oC-30µA
+125oC-60µA
+125oC - 120 µA
-55oC
-55oC
-55oC
-55oC
-55oC 0.64 - mA
-55oC 1.6 - mA
-55oC 4.2 - mA
-55oC - -0.64 mA
-55oC - -2.0 mA
-55oC - -1.6 mA
-55oC - -4.2 mA
LIMITS
UNITSMIN MAX
LIMITS
UNITSMIN MAX
-50mV
-50mV
4.95 - V
9.95 - V
7-878
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