Intersil Corporation CD4021BMS, CD4014BMS Datasheet

CD4014BMS,

CD4021BMS

December 1992

Features

• High Voltage Types (20V Rating)

• Medium Speed Operation 12MHz (Typ.) Clock Rate at VDD-VSS = 10V

• Fully Static Operation

• 8 Master-Slave Flip-Flops Plus Output Buffering and Control Gating

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25

• Noise Margin (Full Package Temperature Range)

• 1V at VDD = 5V

• 2V at VDD = 10V

• 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of `B' Series CMOS Devices

Applications:

CMOS 8-Stage Static Shift Registers

Description

CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous

Serial Input/Serial Output

CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel “JAM” inputs to each register stage. Each register stage is a D-type, master-slave ﬂip-ﬂop. In addition to an output from stage 8, “Q” outputs are also available

from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the P ARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is “forced” when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4014BMS and CD4021BMS are supplied in these 16 lead outline packages:

• Parallel Input/Serial Output Data Queueing

• Parallel to Serial Data Conversion

• General Purpose Register

Pinout

PI-8

Q8 PI-4 PI-3 PI-2 PI-1

VSS

1 2 3 4 5 6 7 8

VDD

PI-7

PI-6

PI-5

SERIAL IN

CLOCK

PARALLEL/SERIAL CONTROL

Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

Functional Diagram

12345678

PARALLEL/SERIAL

CONTROL

SERIAL IN

CLOCK

PAR. IN

VDD

14 1513 1456716

BUFFERED

VSS

OUT

7-80

File Number

3294

Speciﬁcations CD4014BMS, CD4021BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

C to +125oC

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2) Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2) Input Voltage Low

(Note 2) Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55 For TA = +100

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

C to +100oC (Package Type D, F, K). . . . . . 500mW

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

C-10µA

2 +125oC - 1000 µA

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

UNITSMIN MAX

7-81

Speciﬁcations CD4014BMS, CD4021BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

Maximum Clock Input Frequency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 320 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 432 ns

10, 11 +125oC, -55oC - 270 ns

10, 11 +125oC, -55oC 2.22 - MHz

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

4.95 - V

9.95 - V

-3V

7-V

7-82

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