Intersil Corporation CD40193BMS, CD40192BMS Datasheet

December 1992

CD40192BMS
CD40193BMS

CMOS Presettable Up/Down Counters

(Dual Clock With Reset)

Features

• CD40192BMS - BCD Type

• CD40193BMS - Binary Type

• High Voltage Type (20V Rating)

• Individual Clock Lines for Counting Up or Counting
Down

• Synchronous High-Speed Carry and Borrow Propaga­tion Delays for Cascading

• Asynchronous Reset and Preset Capability

• Medium Speed Operation

- fCL = 8MHz (typ.) at 10V

• 5V, 10V and 15V Parametric Ratings

• Standardize Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack­age Temperature Range; 100nA at 18V and +25

o

C

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

• Up/Down Difference Counting

• Multistage Ripple Counting

• Synchronous Frequency Dividers

• A/D and D/A Conversion

• Programmable Binary or BCD Counting

Description

CD40192BMS Presettable BCD Up/Down Counter and the
CD40193BMS Presettable Binary Up/Down Counter each con­sist of 4 synchronously clocked, gated “D” type flip-flops con­nected as a counter. The inputs consist of 4 individual jam lines,
a

PRESET ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET. Four buffered Q
signal outputs as well as
multiple-stage counting schemes are provided.

The counter is cleared so that all outputs are in a low state by a
high on the RESET line. A RESET is accomplished asynchro­nously with the clock. Each output is individually programmable
asynchronously with the clock to the level on the corresponding
jam input when the

The counter counts up one count on the positive clock edge of
the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on the positive clock edge
of the CLOCK DOWN signal provided the CLOCK UP line is
high.

The

CARRY and BORROW signals are high when the counter
is counting up or down. The
clock cycle after the counter reaches its maximum count in the
count-up mode. The
cycle after the counter reaches its minimum count in the count­down mode. Cascading of multiple packages is easily accom­plished without the need for additional external circuitry by tying
the

BORROW andCARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the succeeding counter
package.

The CD40192BMS and CD40193BMS are supplied in these
16-lead outline packages:

Braze Seal DIP *H4W, †H4X
Frit Seal DIP H1F
Ceramic Flatpack *H6P, †H6W

* CD40192B Only †CD40193B Only

CARRY and BORROW outputs for

PRESET ENABLE control is low .

CARRY signal goes low one-half

BORROW signal goes low one-half clock

Pinout

CD40192BMS, CD40193BMS

TOP VIEW

VDD

1

J2

2

Q2

3

Q1

Q3
Q4

VSS

4
5
6
7
8

CLOCK DOWN

CLOCK UP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

16
15

J1
RESET

14
13

BORROW

12

CARRY

11

PRESET ENABLE

10

J3

9

J4

Functional Diagram

PRESET
ENABLE

CLOCK UP

CLOCK DOWN

RESET

7-1419

11

15

J1

1

J2

10

J3

9

J4

5
4

3

Q1

2

Q2

6

Q3

7

Q4

13

BORROW

12

CARRY

14

VDD = 16
VSS = 8

File Number

3363

Specifications CD40192BMS, CD40193BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20V 1 +25oC -100 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20V 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

Thermal Resistance θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW

For TA = +100oC to +125oC (Package Type D, F, K). . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

SUBGROUPS TEMPERATURE

2 +125oC - 1000 µA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

ja

LIMITS

VDD/2

VOL <
VDD/2

θ

jc

UNITSMIN MAX

V

7-1420

Specifications CD40192BMS, CD40193BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTES 1, 2)

Propagation Delay
Clock Up or Clock Down
to Q

Propagation Delay
Reset to Q

Propagation Delay
PE to Q

Propagation Delay
Clock Up to Carry, Clock
Down to Borrow

Propagation Delay

PE to Borrow or Carry

Propagation Delay

Reset to Borrow or Carry

Transition Time TTHL

Maximum Clock Input
Frequency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TPHL1
TPLH1

TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

TPHL3
TPLH3

TPHL4
TPLH4

TPHL5
TPLH5

TPHL6
TPLH6

TTLH

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 320 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

GROUP A

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 675 ns

10, 11 +125oC, -55oC - 675 ns

10, 11 +125oC, -55oC - 540 ns

10, 11 +125oC, -55oC - 432 ns

10, 11 +125oC, -55oC - 810 ns

10, 11 +125oC, -55oC - 810 ns

10, 11 +125oC, -55oC - 270 ns

10, 11 +125oC, -55oC 1.48 - MHz

LIMITS

UNITSMIN MAX

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

+125oC - 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 600 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

-50mV

-50mV

4.95 - V

9.95 - V

UNITSMIN MAX

7-1421

Specifications CD40192BMS, CD40193BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

-55oC

Input Voltage High VIH VDD = 10V , VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

-55oC

Propagation Delay
Clock Up or Down to Q

Propagation Delay
Reset to Q

Propagation Delay
PE to Q

Propagation Delay
Clock Up to Carry, Clock
Down to Borrow

Propagation Delay
PE to Borrow or Carry

Propagation Delay
Reset to Borrow or Carry

Transition Time TTHL1

Maximum Clock Rise and
Fall Time

Minimum Removal Time
Reset or PE

Minimum Pulse Width
Reset

Minimum Pulse Width PE TW VDD = 5V 1, 2, 3 +25oC - 240 ns

TPHL1
TPLH1

TPHL2 VDD = 10V 1, 2, 3 +25oC - 240 ns

TPHL3
TPLH3

TPHL4
TPLH4

TPHL5
TPLH5

TPHL6
TPLH6

TTLH1

TRCL
TFCL

TREM VDD = 5V 1, 2, 3, 5 +25oC - 80 ns

TW VDD = 5V 1, 2, 3 +25oC - 480 ns

VDD = 10V 1, 2, 3 +25oC - 240 ns
VDD = 15V 1, 2, 3 +25oC - 180 ns

VDD = 15V 1, 2, 3 +25oC - 180 ns
VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns
VDD = 10V 1, 2, 3 +25oC - 160 ns
VDD = 15V 1, 2, 3 +25oC - 120 ns

VDD = 10V 1, 2, 3 +25oC - 300 ns
VDD = 15V 1, 2, 3 +25oC - 220 ns
VDD = 10V 1, 2, 3 +25oC - 300 ns
VDD = 15V 1, 2, 3 +25oC - 220 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
VDD = 5V 1, 2, 3, 4 +25oC-15µs
VDD = 10V 1, 2, 3, 4 +25oC-15µs
VDD = 15V 1, 2, 3, 4 +25oC-5µs

VDD = 10V 1, 2, 3, 5 +25oC - 40 ns
VDD = 15V 1, 2, 3, 5 +25oC - 30 ns

VDD = 10V 1, 2, 3 +25oC - 300 ns
VDD = 15V 1, 2, 3 +25oC - 260 ns

VDD = 10V 1, 2, 3 +25oC - 170 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns

-3V

7-V

UNITSMIN MAX

7-1422