Intersil Corporation CD4018BMS Datasheet

November 1994

CD4018BMS

CMOS Presettable

Divide-By- “N” Counter

Features

• High Voltage Type (20V Rating)

• Medium Speed Operation 10MHz (typ.) at VDD - VSS = 10V

• Fully Static Operation

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range;

- 100nA at 18V and 25

• Noise Margin (Over Full Package T emperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of ‘B’ Series CMOS Devices”

Applications

• Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5, 4, 3, 2 Counters

• Fixed and Programmable Counters Greater Than 10

• Programmable Decade Counters

• Divide-By- “N” Counters/Frequency Synthesizers

• Frequency Division

• Counter Control/Timers

Description

CD4018BMS types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter conﬁgurations can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter conﬁgurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018BMS units. The counter is advanced one count at the positive clock-signal transition. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.

The CD4018BMS is supplied in these 16-lead outline packages:

Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

Functional Diagram

JAM INPUTS

“2”

“1”

“3”

VDD

“4”

“5”

97123216

PRESET

Pinout

CD4018BMS

TOP VIEW

VDD

DATA

JAM 1

JAM 2

JAM 3

7 8

VSS

16 15

RESET CLOCK

14 13

JAM 5

PRESET ENABLE

JAM 4

7-350

ENABLE

CLOCK

DATA

RESET

VSS

BUFFERED OUT

File Number

3298

Speciﬁcations CD4018BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

C to +125oC

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2) Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2) Input Voltage Low

(Note 2) Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55 For TA = +100

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

C to +100oC (Package Type D, F, K). . . . . . 500mW

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

C-10µA

2 +125

C - 1000 µA

C -100 - nA

C -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

UNITSMIN MAX

7-351

Speciﬁcations CD4018BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Propagation Delay Clock To Q

Propagation Delay Preset To Q

Propagation Delay Reset To Q

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Propagation Delay Clock To Q

Propagation Delay Preset To Q

Propagation Delay Reset to Q

TPHL1 TPLH1

TPHL2 TPLH2

TPLH3 VDD = 5V, VIN = VDD or GND 9 +25oC - 550 ns

TPHL1 TPLH1

TPHL2 TPLH2

TPLH3 VDD = 10V 1, 2, 3 +25oC - 250 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 550 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns

VDD = 15V 1, 2, 3 +25oC - 180 ns

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 540 ns

10, 11 +125oC, -55oC - 743 ns

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

4.95 - V

9.95 - V

-3V

7-V

7-352

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