Intersil Corporation CD22103A Datasheet

CD22103A

Data Sheet January 1997 File Number

CMOS HDB3 (High Density Bipolar 3) Transcoder for 2.048/8.448Mb/s Transmission Applications

The CD22103A is an LSI SOS integrated circuit which performs the HDB3 transmission coding and reception decoding functions with error detection. It is used in

2.048Mb/s and 8.448Mb/s transmission applications. The CD22103A performs HDB3 coding and decoding for data rates from 50Kb/s to 10Mb/s in a manner consistent with CCITT G703 recommendations.

HDB3 transmission coding/reception decoding with code error detection is performed in independent coder and decoder sections. All transmitter and receiver inputs/outputs are TTL compatible.

The HDB3 transmitter coder codes an NRZ binary unipolar input signal (NRZ-IN) and a synchronous transmissionclock (CTX) into two HDB3 binary unipolar RZ output signals (+HDB3 OUT, -HDB3 OUT). The TTL compatible output signals +HDB3 OUT, -HDB3 OUT are externally mixed to generate ternary bipolar HDB3 signals for driving transmission lines.

The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).

The CD22103A operates with a 5V ±10% power supply voltage over the full military temperature range at data rates from 50Kb/s up to 10Mb/s.

Block Diagram

HDB3/AMI

NRZ-IN

ENCODER

CTX

TRANSMITTER

CODER

+HDB3 OUT

-HDB3 OUT

CKR

1310.3

Features

• HDB3 Coding and Decoding for Data Rates from 50Kb/s to 10Mb/s in a Manner Consistent with CCITT G703 Recommendations

• HDB3/AMI Transmission Coding/ReceptionDecodingwith Code Error Detection is Performed in Independent Coder and Decoder Sections

• All Transmitter and Receiver Inputs/Outputs are TTL Compatible

• Internal Loop Test Capability

• Pin and Functionally Compatible with Type MJ1471

Ordering Information

PART

NUMBER

CD22103AD -55 to 125 16 Ld SBDIP D16.3 CD22103AE -40 to 85 16 Ld PDIP E16.3

TEMP.RANGE

(oC) PACKAGE PKG. NO.

Pinout

CD22103A (PDIP, SBDIP)

TOP VIEW

NRZ-IN

CTX

HDB3/AMI

NRZ-OUT

CRX

RAIS

AIS

1 2 3 4 5 6 7 8

+HDB3 OUT

15 14

-HDB3 OUT +HDB3 IN

LTE

-HDB3 IN

CKR

ERR

LTE

+HDB3 IN

-HDB3 IN CRX

DECODER

RAIS

REQUIRES CLOCK RECOVERY CIRCUIT

RECEIVER DECODER

ERROR

DETECT

NRZ-OUT

ERR

AIS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

CD22103A

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD)

(Voltages referenced to VSS Terminal) . . . . . . . . . . . . . -0.5 to 8V

Supply Voltage Range

For TA = Full Package Temperature Range. . . . . . . . . . . . 4.5V to 5.5V

Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V

Input Current (Any One Input) . . . . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Power Dissipation

For TA = -40oC to 60oC (Package Type E). . . . . . . . . . . . .500mW

For TA = 60oC to 85oC

(Package Type E). . . . . . . . Derate Linearly 12mW/oC to 200mW

For TA = -55oC to 100oC (Package Type D). . . . . . . . . . . .500mW

For TA = 100oC to 125oC

(Package Type D). . . . . . . . Derate Linearly 12mW/oC to 200mW

Device Dissipation per Output Transistor

For TA = Full Package Temperature Range (All Types) . . . . . 100mW

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . -65oC ≤ TA≤ 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

Operating Conditions

Temperature Range

Package Type D . . . . . . . . . . . . . . . . . . . . . . . -55oC ≤ TA≤ 125oC

Package Type E . . . . . . . . . . . . . . . . . . . . . . . . -40oC ≤ TA≤ 85oC

Electrical Speciﬁcations V

= 5V ±10%, TA = 25oC

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

STATIC SPECIFICATIONS

Quiescent Device Current I

Operating Device Current f HDB3 Output Low (Sink) Current I HDB3 Output High (Source) Current I All Other Outputs Low (Sink) Current I All Other Outputs High (Source) Current I Input Low Current I Input High Current I Input Low Voltage V Input High Voltage V Input Capacitance I

Electrical Speciﬁcations T

= -40oC to 85oC for Plastic Pac kage; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V;

OL1 OH1 OL2 OH2

IL IH

CL= 15pF

PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS

DYNAMIC INPUT

CTX, CRX Input Frequency f CTX, CRX Input Rise Time t

Fall Time t

NRZ-IN to CTX

Data Setup Time t Data Hold Time t

HDB3 IN to CRX

Data Setup Time t Data Hold Time t

- - 100 µA

= 10MHz - - 8 mA

VOL = 0.5V 1.6 - - mA VOH = 2.8V -10 - - mA VOL = 0.5V 1.6 - - mA VOH = 2.8V -1.6 - - mA

---1µA

--1µA

- - 0.8 V

2--V

--5pF

CTX

, f

RCL FCL

S H

CRX

3--1µs 3--1µs

315- - ns 315- - ns

415- - ns 30- - ns

0.05 - 10 MHz

CD22103A

Electrical Speciﬁcations T

PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS

CRX to CKR (CRX = 8.448MHz)

Pretrigger t Delay t

DYNAMIC OUTPUT

Transmitter Coder, CTX to HDB3 OUT:

Data Propagation Delay Time t Handling Delay Time t

HDB3 OUT Output Pulse Width (Clock duty cycle = 50%)

fCL = 2.048MHz t fCL = 8.448MHz t

Receiver Decoder CRX to NRZ OUT:

Data Propagation Delay Times t Handling Delay Time t

HDB3 IN to CKR HDB3 Propagation Delay Time

LTE = 0 t LTE = 1 4 - - 30 ns

= -40oC to 85oC for Plastic Pac kage; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V;

CL= 15pF (Continued)

P D

DD HD

W W

DD HD

IN CKR

5--20ns 5--20ns

3--90ns 1 - 4 - Clock Period

3 238 - 260 ns 353-65

4--90ns 2 - 4 - Clock Period

4--65ns

Functional Description

The CD22103A is designed to code and decode HDB3 signals which are coded as binary digital signals (NRZ-lN) and (+HDB3 IN, -HDB3 IN), accompanied by sampling clocks (CTX) and (CRX). The two binary coded HDB3 outputs, (+HDB3 OUT, -HDB3 OUT) may be externally mixed to create the ternary HDB3 signals (See Figure 1).

The two binary HDB3 input signals have been split from the input ternary HDB3 in an external line receiver.

The receiver decoder converts binary unipolar inputs (+HDB3 IN,

-HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT).

Received signals not consistent with HDB3 coding rules are detected as errors. The receiver error output (ERR) is active high during one CRX period of each bit of receiveddata thatis inconsistent with HDB3 coding rules.

An input string consisting of all ones (or marks) is detected and signaled by a high level at the Alarm Signal (AIS) output. The AIS output is set to a high level when less than three zeros are received during two consecutiveperiods of the Reset Alarm Inhibit Signal (RAIS). The AIS output is subsequently reset to a low level when three or more zeros are received during two periods of the reset signal (

A diagnostic Loop-T estMode may be entered by driving the Loop Test Enable Input (LTE) high. In this mode the HDB3 transmitter outputs (+HDB3 OUT, -HDB3 OUT) are internally connected to

RAIS).

the HDB3 receiver inputs, and the e xternal HDB3 receiver inputs, and the external HDB3 receiver inputs (+HDB3 IN, -HDB3 IN) are disabled. The NRZ binary output signal (NRZ - OUT) corresponds to the NRZ binary input signal (NRZ - IN) delayed by approximately 8 clock periods.

The Clock Receiver Output (CKR) is the product of the two HDB3 input signals or-ed together.The CRX clocksignal may be derived from the CKR signal with e xternal clock extraction circuitry . In the Loop Test Mode (L TE= 1) CKR is the product of the +HDB3 OUT and -HDB3 OUT signals or-ed together.

The CD22103A may also be used to perform the AMI to NRZ coding/decoding function. To use the CD22103A in this mode, the HDB3/AMI control input is driven low .

Error Detection

Received HDB3/AMl binary input signals are checked for coding violations, and an error signal (ERR) is generated as described below.

• HDB3 Signals HDB3/AMl = High

The error signal (ERR) is ﬂagged high for one CTX period if a violation pulse (±V) is received of the same polarity as the last received violation pulse.

A violation pulse (±V) is considered a reception error and does not cause replacement of the last string of 4 bits to zeros, if:

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