Intersil Corporation CA5160 Datasheet

CA5160

NOT RECOMMENDED FOR NEW DESIGNS

September 1998

Amplifiers with MOSFET Input/CMOS Output

Features

• MOSFET Input Stage

- Very High Z

- Very Low I

; 1.5TΩ (1.5 x 1012Ω) (Typ)

I

; 5pA (Typ) at 15V Operation

I

2pA (Typ) at 5V Operation

• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be
Swung 0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails

• CA5160 Has Full Military Temperature Range
Guaranteed Specifications for V+ = 5V

• CA5160 is Guaranteed to Operate Down to 4.5V for A

• CA5160 is Guaranteed Up to ±7.5V

Applications

• Ground Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long Duration Timers/Monostables

• Ideal Interface With Digital CMOS

• High Input Impedance Wideband Amplifiers

• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)

• Wien-Bridge Oscillators

• Voltage Controlled Oscillators

• Photo Diode Sensor Amplifiers

• 5V Logic Systems

• Microprocessor Interface

4MHz, BiMOS Microprocessor Operational

Description

CA5160 is an integrated circuit operational amplifier that com­bines the advantage of both CMOS and bipolar transistors on
a monolithic chip. The CA5160 is a frequency compensated
version of the popular CA5130 series. It is designed and guar­anteed to operate in microprocessor or logic systems that use
+5V supplies.

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input impedance,
very low input current, and exceptional speed performance.
The use of PMOS field effect transistors in the input stage
results in common-mode input voltage capability down to 0.5V
below the negative supply terminal, an important attribute in
single supply applications.

OL

A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.

The CA5160 operates at supply voltages ranging from +5V to
+16V, or ±2.5V to±8V when using split supplies, and have ter­minals for adjustment of offset voltage for applications requir­ing offset-null capability. Terminal provisions are also made to
permit strobing of the output stage. It has guaranteed specifi­cations for 5V operation over the full military temperature
range of -55

Ordering Information

PART NUMBER

CA5160E -55 to 125 8 Ld PDIP E8.3
CA5160M96

(5160)

o

C to 125oC.

(BRAND)

TEMP.

RANGE (oC) PACKAGE

-55 to 125 8 Ld SOIC
Tape and Reel

PKG.

NO.

M8.15

Pinout

CA5160 (PDIP, SOIC)

TOP VIEW

OFFSET NULL

INV. INPUT

NON INV. INPUT

NOTE: CA5160 devices have an on-chip frequency compensation network. Supplementary phase-compensation or frequency roll-off
(if desired) can be connected externally between terminals 1 and 8.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1

2

3

4

V-

-

+

3-1

8

STROBE

7

V+

6

OUTPUT

5

OFFSET NULL

File Number

1924.4

CA5160

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V

Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA

Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. Short circuit may be applied to ground or to either supply.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 120 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 165 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage V
Input Offset Current I
Input Current I

= 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified

A

TEST

CONDITIONS

IO

IO

I

VO = 2.5V - 2 10 mV
VO = 2.5V - 0.1 10 pA
VO= 2.5V - 2 15 pA

CA5160

UNITSMIN TYP MAX

Common Mode Rejection Ratio CMRR VCM = 0 to 1V 70 80 - dB

VCM = 0 to 2.5V 60 69 - dB

Common Mode Input Voltage Range V

+ 2.5 2.8 - V

lCR

V

- - -0.5 0 V

lCR

Power Supply Rejection Ratio PSRR ∆V+ = 1V; ∆V- = 1V 55 67 - dB
Large Signal Voltage

Gain (Note 3)

Source Current I
Sink Current I
Maximum Output V oltage VOM+V

VO = 0.1 to 4.1V A
VO = 0.1 to 3.6V

SOURCE

OL

SINK

OUT

RL= ∞ 95 117 - dB
R

L

=10kΩ

85 102 - dB

VO = 0V 1.0 3.4 4.0 mA
VO = 5V 1.0 2.2 4.0 mA

RL = ∞ 4.99 5 - V
VOM- - 0 0.01 V
VOM+R

= 10kΩ 4.4 4.7 - V

L

VOM- - 0 0.01 V
VOM+R

= 2kΩ 2.5 3.3 - V

L

VOM- - 0 0.01 V

Supply Current I

SUPPLY

I

SUPPLY

VO = 0V - 50 100 µA

VO = 2.5V - 320 400 µA

NOTE:

3. For V+ = 4.5V and V- = GND; V

= 0.5V to 3.2V at RL = 10kΩ.

OUT

Electrical Specifications T

= -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified

A

PARAMETER SYMBOL

Input Offset Voltage V
Input Offset Current I

TEST

CONDITIONS

IO

IO

VO= 2.5V - 3 15 mV
VO= 2.5 V - 0.1 10 nA

CA5160

UNITSMIN TYP MAX

3-2

CA5160

Electrical Specifications T

PARAMETER SYMBOL

Input Current I

= -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified (Continued)

A

TEST

CA5160

CONDITIONS

VO= 2.5V - 2 15 nA

I

UNITSMIN TYP MAX

Common Mode Rejection Ratio CMRR VCM = 0 to 1V 60 80 - dB

VCM = 0 to 2.5V 50 75 - dB

Common Mode Input Voltage Range V

+ 2.5 2.8 - V

lCR

V

- - -0.5 0 V

lCR

Power Supply Rejection Ratio PSRR ∆V+ = 2V 40 60 - dB
Large Signal Voltage Gain

(Note 4)

Source Current I
Sink Current I
Maximum Output V oltage VOM+V

VO = 0.1 to 4.1V A

OL

R

= ∞ 90 110 - dB

L

VO = 0.1 to 3.6V RL=10kΩ 75 100 - dB

SOURCEVO

SINK

OUT

= 0V 0.6 - 5.0 mA
VO = 5V 0.6 - 5.0 mA
R

= ∞ 4.99 5 - V

L

VOM- - 0 0.01 V
VOM+R

= 10kΩ 4.0 4.3 - V

L

VOM- - 0 0.01 V
VOM+R

= 2kΩ 2.0 2.5 - V

L

VOM- - 0 0.01 V

Supply Current VO = 0V I

VO = 2.5V I

SUPPLY
SUPPLY

- 170 220 µA

- 410 500 µA

NOTE:

4. For V+ = 4.5V and V- = GND; V

= 0.5V to 3.2V at RL = 10kΩ.

OUT

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage V
Input Offset Current I
Input Current I
Large Signal Voltage Gain A

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

TEST

CONDITIONS

IO

IO

OL

VS= ±7.5V - 6 15 mV
VS= ±7.5V - 0.5 30 pA
VS= ±7.5V - 5 50 pA

I

VO = 10V

P-P

RL = 2kΩ

CA5160

UNITSMIN TYP MAX

50 320 - kV/V

94 110 - dB
Common Mode Rejection Ratio CMRR 70 90 - dB
Common Mode Input Voltage Range V

lCR

Power Supply Rejection Ratio PSRR ∆V+ = 1V;∆V- = 1V

10 -0.5 to 12 0 V

- 32 320 µV/V

VS = ±7.5V

Maximum Output
Voltage

VOM+V

OUT

RL = 2kΩ 12 13.3 - V
VOM- - 0.002 0.01 V
VOM+R

= ∞ 14.99 15 - V

L

VOM- - 0 0.1 V

3-3

CA5160

Electrical Specifications T

PARAMETER SYMBOL

Maximum Output
Current

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued)

A

CA5160

UNITSMIN TYP MAX

IOM+ (Source) I

TEST

CONDITIONS

O

VO = 0V 12 22 45 mA
IOM- (Sink) VO = 15V 12 20 45 mA

Supply Current I+ RL = ∞, VO = 7.5V - 10 15 mA

RL = ∞, VO = 0V - 2 3 mA

Input Offset Voltage Temperature Drift ∆VIO/∆T-8-µV/oC

Electrical Specifications For Design Guidance, At T

= 25oC, V

A

= ±7.5V, Unless Otherwise Specified

SUPPLY

TYPICAL
VALUES

PARAMETER SYMBOL TEST CONDITIONS

UNITSCA5160

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or 4 and 1 ±22 mV
Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e

I

f = 1MHz 4.3 pF

I

BW = 0.2MHz, RS = 1MΩ 40 µV

N

1.5 TΩ

BW = 0.2MHz, RS = 10MΩ 50 µV

Equivalent Input Noise Voltage e

RS = 100Ω, 1kHz 72 nV/√Hz

N

RS = 100Ω, 10kHz 30 nV/√Hz

Unity Gain Crossover F requency f

T

4 MHz
Slew Rate SR 10 V/µs
Transient Response Rise Time t

CC = 25pF, RL = 2kΩ (Voltage Follower) 0.09 µs

R

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4V

)tSCC = 25pF, RL = 2kΩ, (Voltage Follower) 1.8 µs

P-P

Block Diagram

+
3

INPUT

2

-

5 1

OFFSET

NULL

A

V

200µA 1.35mA 200µA

BIAS CKT.

A

≈

≈5X

COMPENSATION

(WHEN DESIRED)

V

6000X

C

C

7

8mA
(NOTE 5)

0mA
(NOTE 6)

V+

NOTE:

5. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.

6. Total supply v oltage (f or indicated voltage
gains) = 15V with output terminal driven to
either supply rail.

OUTPUT

A

≈30X

V

8

STROBE

6

4

V-

3-4

Schematic Diagram

BIAS CIRCUIT “CURRENT SOURCE

CURRENT SOURCE

FOR Q6 AND Q

7

CA5160

LOAD” FOR Q

7

11

V+

Q

R

3

1kΩ

Q

9

R

5

1kΩ

OFFSET NULL

Q

2

Q

4

SECOND
STAGE

7

SUPPLEMENTARY
COMP IF DESIRED

2kΩ

30
pF

Q

11

R

4

1kΩ

10

R
1kΩ

D

6

D

6

Q

6

7

Q

Q

Z

1

8.3V
R

1

40kΩ

R

5kΩ

NON-INV.

INPUT

INV. INPUT

1

D

1

D

2

D

3

D

4

2

INPUT STAGE

D

5

3

+

2

-

NOTE: Diodes D5 through D7 provide gate oxide protection for MOSFET Input Stage .

Q

3

Q

5

OUTPUT
STAGE

Q

Q

STROBING

8

OUTPUT

6

12

4815

Application Information

Circuit Description

Refer to the block diagram of the CA5160 CMOS Operational
Amplifier. The input terminals may be operated down to 0.5V
below the negative supply rail, and the output can be swung
very close to either supply rail in many applications. Conse­quently, the CA5160 circuit is ideal for single supply operation.
Three class A amplifier stages, having the individual gain
capability and current consumption shown in the block dia­gram, provide the total gain of the CA5160. A biasing circuit
provides two potentials for common use in the first and sec­ond stages. Terminals 8 and 1 can be used to supplement the
internal phase compensation network if additional phase com­pensation or frequency roll-off is desired. Terminals 8 and 4
can also be used to strobe the output stage into a low quies­cent current state. When Terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of essentially
zero current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis­tance presented to the amplifier is very high (e.g., when the
amplifier output is used to drive CMOS digital circuits in com­parator applications).

Input Stages

The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q
sistors (Q
resistors R

, Q7) working into a mirror pair of bipolar tran-

6

, Q10) functioning as load resistors together with

9

through R6. The mirror pair transistors also func-

3

tion as a differential-to-single-ended conv erter to provide base
drive to the second-stage bipolar transistor (Q

). Offset null-

11

ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome­ter slider arm to Terminal 4.

Cascode-connected PMOS transistors Q

, Q4, are the

2

constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D

through D7 provide gate-

5

oxide protection against high voltage transients, including
static electricity during handling for Q

and Q7.

6

Second Stage

Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q

11

and its cascode-connected load resistance provided by

3-5

CA5160

PMOS transistors Q3 and Q5. The source of bias potentials
for these PMOS transistors is described later. Miller Effect
compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩ resistor connected between the
base and collector of transistor Q

. These internal compo-

11

nents provide sufficient compensation for unity gain opera­tion in most applications. However, additional compensation,
if desired, may be used between Terminals 1 and 8.

Bias-Source Circuit

At total supply voltages, somewhat above 8.3V, resistor R
and zener diode Z1 serve to establish a voltage of 8.3V across
the series connected circuit, consisting of resistor R
D

through D4, and PMOS transistor Q1. A tap at the junction

1

of resistor R
about 4.5V for PMOS transistors Q

and diode D4 provides a gate bias potential of

1

and Q5 with respect to

4

, diodes

1

Terminal 7. A potential of about 2.2V is developed across
diode connected PMOS transistor Q
7 to provide gate bias for PMOS transistors Q
should be noted that Q
Q

. Since transistors Q1, Q2 and Q3 are designed to be iden-

3

is “mirror connected” to both Q2 and

1

tical, the approximately 200µA current in Q
similar current in Q

and Q3 as constant current sources for

2

with respect to Terminal

1

and Q3. It

2

establishes a

1

both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode

Z

becomes non-conductive and the potential, developed

1

across series connected R

, D1-D4, and Q1 varies directly

1

with variations in supply voltage. Consequently, the gate bias
for Q

, Q5 and Q2, Q3 varies in accordance with supply

4

voltage variations. This variation results in deterioration of the
power supply rejection ration (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about

4.5V results in seriously degraded performance.

Output Stage

The output stage consists of a drain loaded inverting ampli­fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain loaded amplifier, its gain is depen­dent upon the load impedance. The transfer characteristics
of the output stage for a load returned to the negative supply
rail are shown in Figure 20. Typical op-amp loads are readily
driven by the output stage. Because large signal excursions
are nonlinear, requiring feedback for good waveform repro­duction, transient delays may be encountered. As a voltage
follower, the amplifier can achieve 0.01% accuracy levels,
including the negative supply rail.

Offset Nulling

Offset voltage nulling is usually accomplished with a 100,000Ω
potentiometer connected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Terminal 4. A fine offset
null adjustment usually can be affected with the slider arm posi­tioned in the mid point of the potentiometer’s total range .

Input Current Variation with Common Mode Input Voltage

As shown in the Table of Electrical Specifications, the input
current for the CA5160 Series Op Amps is typically 5pA at

T

= 25oC when Ter minals 2 and 3 are at a common-mode

A

potential of +7.5V with respect to negative supply Terminal

4. Figure 1 contains data showing the variation of input
current as a function of common-mode input voltage at
T

=25oC. These data show that circuit designers can

A

advantageously exploit these characteristics to design
circuits which typically require an input current of less than
1pA, provided the common-mode input voltage does not
exceed 2V. As previously noted, the input current is
essentially the result of the leakage current through the gate­protection diodes in the input circuit and, therefore, a

2

function of the applied voltage. Although the finite resistance
of the glass terminal-to-case insulator of the metal can
package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate­protection network functions as if it is connected to Ter minal
4 potential, and the metal can case of the CA5160 is also
internally tied to Terminal 4, input terminal 3 is essentially
“guarded” from spurious leakage currents.

10

TA = 25oC

7.5

V+

CA5160

4

7

8

V-

5

INPUT VOLTAGE (V)

2.5

0

-101234567
INPUT CURRENT (pA)

FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE

VOLTAGE

PA

2

3

V

IN

Input Current Variation with Temperature

The input current of the CA5160 series circuits is typically
5pA at 25

o

C. The major portion of this input current is due to
leakage current through the gate protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10
increase in temperature. Figure 2 provides data on the
typical variation of input bias current as a function of
temperature in the CA5160.

In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA5160. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat­sinking can also very markedly reduce and stabilize input
current variations.

15V

TO
5V

0V

TO

-10V

6

o

C

3-6