Intersil Corporation CA3450 Datasheet

OBSOLETE PRODUCT

CEMENT

CA3450

NO RECOMMENDED REPLA

Call Central Applications 1-800-442-7747

or email: [e-mail]

220MHz, Video Line Driver, High Speed
Operational Amplifier

The CA3450 is a large signal video line driver and high
speed operational amplifier capable of driving 50Ω
transmission lines and flash A/Ds. The uncompensated unity
gain crossing occurs at 230MHz without load. It can operate
at dual or single supplies of ±7.25V or 14.5V, respectively.
The CA3450 can be compensated with a single capacitor
network. It has output drive capability of 75mA SINK or
SOURCE. The CA3450 is capable of driving Flash A/Ds in
video or high speed instrumentation (accurate) applications
with bandwidth up to 10MHz. Offset voltagenullingterminals
are also available.

Pinout

CA3450

(PDIP)

TOP VIEW

OFFSET NULL

OFFSET NULL

NC

- INPUT

V
V+
V+

1
2
3
4

V-

5

V-

6

O

7
8

16
15
14
13
12
11
10

9

NC
+ INPUT
V­V­COMP
NC
COMP

January 1999 File Number 1732.5

Features

• High Open Loop Gain at Video Frequencies

-A

. . . . . . . . . . . . . . . . . . . . . . . . . .>40dB at f = 5MHz

OL

• Power Bandwidth of 10MHz . . . . . . . A

• Slew Rate at Full Load. . . . . . . . . . . . . 330V/µs (A

= 220MHz; CC= 0pF With a Load of 50Ω ||20pF|| 1MΩ

•f

T

= 5; VO = ±3.5V

CL

V

≥ 10)

(Scope Input)

•V

= ±4.1V Into 75Ω

OUT

• Offset Null Terminals

Applications

• Video Line Driver

• High Frequency Unity Gain Buffer

• Pulse Amplifier

• High Speed Comparator

• High Frequency Oscillator and Video Amplifiers

• Driver for A/Ds in Video Applications . . . . . . . .10MHz BW

Part Number Information

TEMP.

PART NUMBER

CA3450E -40 to 85 16 Ld PDIP E16.3

RANGE (oC) PACKAGE

PKG.

NO.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

Block Diagram

+IN
14

3

-IN
INPUT CURRENT
COMPENSATED
DIFFERENTIAL
AMPLIFIER

+

X180

-

161

CA3450

BIAS CIRCUIT

DC LEVEL
SHIFT
STAGE

7V+ 8V+

X0.50 X18

OUTPUT POWER
DRIVER AND
OUTPUT POWER
STAGE

1254119

6

OUTPUT

13

Schematic Diagram

D

1

Q

2

Q

1

R

1

100K

Q

R

780

R

10

3.2K

Q

3

V+

Q

26

R

11

24

9

3k

Q

25

D

7

R

12

250

Q

Q

R
860

Q

27

28

13

Q

5

4

INVERTING

INPUT

C

7

Q

R
860

OFFSET

NULL

D

2

6

Q

R

Q

29

14

Q

8

C

1

Q

10

Q

7

21Q22

140

Q

30

R
130

Q

23

R

3

Q

15

20

Q

2

PHASE

COMP

FREQUENCY

COMPENSATION

C

2

Q

11

V-

143

NON-

INVERTING

INPUT

31

R

16

860

V-

11 7

Q

9

Q

12

D

3

Q

8

14

C

3

Q

Q

15

Q

16

17

V-

D

4

Q

8.5K

32

R

17

500

R

5

C

2K

R

4

R
2K

R

18

200

4

6

C

5

Q

Q

33

R

19

100

34

R
170

D
D

20

C

5
6

6

R

8

30

D

10

Q

35

Q

36

R

21

270

Q

18

D

9

Q

37

R
250

V+V+

Q

19

R

7

6

6

9

FREQUENCY
COMPEN­SATION

Q

38

22

OUTPUT

1

16

4, 5, 12, 13

V-

2

CA3450

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . 14.5V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V

Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Electrical Specifications C

PARAMETER SYMBOL TEST CONDITIONS

= 5pF, V

C

= ±6V, Unless Otherwise Specified

SUPPLY

TEMP.

o

C) MIN TYP MAX UNITS

(

DC

Input Offset Voltage |V

|25-820mV

IO

Full - 10 35 mV
Input Bias current |IIB| 25 - 100 400 nA
Input Offset Current |I
Open Loop DC Gain A

| 25 - 50 200 nA

IO

V

OL

= ±2.5V, RL = 50Ω 25 60 70 - dB

OUT

Full 55 - - dB
Power Supply Rejection Ratio PSRR ∆V = ±1V 25 55 65 - dB
Common Mode Rejection Ratio CMRR V
Common Mode Input Range V

ICR

= ±3.5V 25 50 60 - dB

ICR

25 ±3.5 ±3.7 - V

Full ±3.0 - - V
Supply Current I+ 25 - 30 40 mA

Full - - 50 mA

DYNAMIC

-3dB Bandwidth

= 1 (See Figure 2)

A

V

CC = 5pF

Bandwidth (Unity Gain Crossing)

= Open Loop

A

V

CC = 0 (See Figure 1)

Bandwidth (Unity Gain Crossing)

= 10, CC = 0pF

A

V

R

FEEDBACK

R

PIN 3 - G

= 450Ω

= 50Ω (See Figure 2)

No Load 25 - 200 - MHz
R

= 1MΩ||20pF 25 - 190 - MHz

L

= 50Ω||20pF 25 - 185 - MHz

R

L

No Load 25 210 230 - MHz

= 20pF||1MΩ 25 180 200 - MHz

R

L

R

= 50Ω||20pF 25 180 220 - MHz

L

No Load 25 200 210 - MHz
50Ω 25 175 190 - MHz
1M||20pF 25 180 195 - MHz
50Ω||1M||20pF 25 170 188 - MHz

Transient Response, Overshoot
(See Figure 3)

OS A

= 1, CC = 5pF RL = 50Ω||20pF 25 - 30 - %

V

No Load 25 - 20 - %

AV≥10, CC = 0pF, RL = 50Ω||20pF 25 - 10 - %

Settling Time (See Figure 5)
(2V Step, R

= 50Ω||20pF)

L

t

S

AV = -1, CC = 5pF, 0.1%, 10 Bits 25 - 35 - ns

= 1, CC = 5pF, 0.1%, 10 Bits 25 - 50 - ns

A

V

A

= 10, CC = 0pF, 0.1%, 10 Bits 25 - 35 - ns

V

= 10, CC = 0pF, 1.0%, 7 Bits 25 - 25 - ns

A

V

3