Intersil Corporation CA3318 Datasheet

August 1997

CA3318

CMOS Video Speed,

8-Bit, Flash A/D Converter

Features

• CMOS Low Power with SOS Speed (Typ). . . . . . . . 150mW

• Parallel Conversion Technique

• 15MHz Sampling Rate (Conversion Time) . . . . . . .67ns

• 8-Bit Latched Three-State Output with Overflow Bit

• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB

• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V

• 2 Units in Series Allow 9-Bit Output

• 2 Units in Parallel Allow 30MHz Sampling Rate

Applications

• TV Video Digitizing (Industrial/Security/Broadcast)

• High Speed A/D Conversion

• Ultrasound Signature Analysis

• Transient Signal Analysis

• High Energy Physics Research

• General-Purpose Hybrid ADCs

• Optical Character Recognition

• Radar Pulse Analysis

• Motion Signature Analysis

• µP Data Acquisition Systems

Description

The CA3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.

The CA3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When
operated from a 5V supply at a clock frequency of 15MHz,
the typical power consumption of the CA3318 is 150mW.

The intrinsic high conversion rate makes the CA3318 ideally
suited for digitizing high speed signals. The overflow bit
makes possible the connection of two or more CA3318s in
series to increase the resolution of the conversion system. A
series connection of two CA3318s may be used to produce a
9-bit high speed converter. Operation of two CA3318s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 15MHz to 30MHz).

256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to
produce the parallel bit outputs in the CA3318.

255 comparators are required to quantize all input voltage
levels in this 8-bit con verter, and the additional comparator is
required for the overflow bit.

Ordering Information

PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE (oC) PACKAGE PKG. NO.

CA3318CE ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld PDIP E24.6
CA3318CM ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SOIC M24.3
CA3318CD ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SBDIP D24.6

Pinout

CA3318

(PDIP, SBDIP, SOIC)

TOP VIEW

(LSB) B1

(MSB) B8

OVERFLOW

(DIG. GND) V
(DIG. SUP.) V

1
2

B2
B3

3

B4

4
5

B5
B6

6

B7

7
8
9

1

10

/4R

11

SS

12

DD

24

VAA+ (ANA. SUP.)

3

23

/4R
22
21
20
19
18
17
16
15
14
13

+

V

REF

V

IN

p
PHASE
CLK

- (ANA. GND)

V

AA

V

IN

V

-

REF

CE1
CE2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

4-9

File Number 3103.1

Functional Block Diagram

CA3318

VAA+

24

V

IN

21

V

REF

22

3

/4 REF

23

1

/2 REF

20

1

/4REF

10

V

IN

16

V

REF

15

CLOCK

18

PHASE

19

-

V

AA

17

+

1

/2 R

R = 2Ω

= 7Ω

= 30Ω

= 4Ω

R

≅2K

-

1

/2 R

ANALOG
SUPPLY

R

R

R

R

R

R

≅50K

ANALOG
GND

φ2 φ1 φ1 φ1 φ1 φ2 φ1

COUNT

256

COUNT

193

COUNT

129

COUNT

65

COUNT

1

ENCODER

LOGIC

ARRAY

CAB

# 256

CAB

# 193

CAB

# 129

CAB

# 65

CAB

(NOTE 1)

COMPARATOR #1

DQ

LATCH

256

DQ

LATCH

DQ

LATCH

DQ

LATCH

DQ

LATCH

1

DQ

LATCH

256

DQ

LATCH

DQ

LATCH

DQ

LATCH

DQ

LATCH

11

φ1 (AUTO BALANCE)

φ2 (SAMPLE UNKNOWN)

NOTE:

1. Cascaded Auto Balance (CAB).

DIGITAL
SUPPLY

OUTPUT

REGISTER

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DQ
CLK

DIGITAL

THREE-

STATE

DRIVERS

GND

V

DD

12

OVER-

FLOW

9

BIT 8

(MSB)

8

BIT 7

7

BIT 6

6

BIT 5

5

BIT 4

4

BIT 3

3

BIT 2

2

BIT 1

(LSB)

1

CE1

14

CE2

13

V

SS

11

4-10

CA3318

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V

(Referenced to VSS or VAA- Terminal, Whichever is More Negative)

Input Voltage Range

CE2 and CE1 . . . . . . . . . . . . . . . . . . . . VAA- -0.5V to VDD + 0.5V

Clock, Phase, V
Clock, Phase, V
VIN,3/4 REF, V

-,1/2 Ref. . . . . . . VAA- -0.5V to VAA+ + 0.5V

REF

-,1/4 Ref. . . . . . . . VSS- -0.5V to VDD + 0.5V

REF

+ . . . . . . . . . . . . . .VAA- -0.5V to VAA- + 7.5V

REF

Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V

Bits 1-8, Overflow (Outputs Off)

DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Clock, Phase, CE1, CE2, VIN, Bits 1-8, Overflow

Operating Conditions

Operating Voltage Range (VDD or VAA+). . . 4V (Min) to 7.5V (Max)

Recommended VAA+ Operating Range. . . . . . . . . . . . . . . VDD±1V

Recommended VAA- Operating Range . . . . . . . . . . . . . . . VSS±1V

Operating Temperature Range (TA) . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

SBDIP Package. . . . . . . . . . . . . . . . . . . . 60 22

PDIP Package. . . . . . . . . . . . . . . . . . . . . 60 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . . . 75 N/A

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .265oC

(SOIC - Lead Tips Only)

Electrical Specifications At 25

o

C, VAA+ = VDD = 5V, V

+ = 6.4V, V

REF

- = VAA- = VSS, CLK = 15MHz,

REF

All Reference Points Adjusted, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 8 - - Bits
Integral Linearity Error - - ± 1.5 LSB
Differential Linearity Error - - +1, -0.8 LSB
Offset Error, Unadjusted

Gain Error Unadjusted

VIN = V
VIN = V

- +1/2 LSB

REF

+ -1/2 LSB

REF

-0.5 4.5 6.4 LSB

-1.5 0 1.5 LSB

DYNAMIC CHARACTERISTICS

Maximum Input Bandwidth (Note 1) CA3318 2.5 5.0 - MHz
Maximum Conversion Speed CLK = Square Wave 15 17 - MSPS
Signal to Noise Ratio (SNR) fS = 15MHz, fIN = 100kHz - 47 - dB

RMSSignal

--------------------------------

=

RMSNoise

fS = 15MHz, fIN = 4MHz - 43 - dB

Signal to Noise Ratio (SINAD) fS = 15MHz, fIN = 100kHz - 45 - dB

RMSSignal

------------------------------------------------------------

=

RMSNoise+Distortion

fS = 15MHz, fIN = 4MHz - 35 - dB

Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - -46 - dBc

fS = 15MHz, fIN = 4MHz - -36 - dBc

Effective Number of Bits (ENOB) fS = 15MHz, fIN = 100kHz - 7.2 - Bits

fS = 15MHz, fIN = 4MHz - 5.5 - Bits
Differential Gain Error Unadjusted - 2 - %
Differential Phase Error Unadjusted - 1 - %

ANALOG INPUTS

Full Scale Range, VIN and (V
Input Capacitance, V

IN

Input Current, VIN, (See Text) VIN = 5V, V

REF

+) - (V

-) Notes 2, 4 4 - 7 V

REF

-30- pF

+ = 5V - - 3.5 mA

REF

REFERENCE INPUTS

Ladder Impedance 270 500 800 Ω

4-11

CA3318

Electrical Specifications At 25

o

C, VAA+ = VDD = 5V, V

+ = 6.4V, V

REF

- = VAA- = VSS, CLK = 15MHz,

REF

All Reference Points Adjusted, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS

Low Level Input Voltage, V

CE1, CE2 Note 4 - - 0.2V
Phase, CLK Note 4 - - 0.2V

High Level Input Voltage, V

CE1, CE2 Note 4 0.7V
Phase, CLK Note 4 0.7V

OL

DD
AA

IN

DD
AA

--V

--V

V
V

Input Leakage Current, II (Except CLK Input) Note 3 - ±0.2 ±5 µA
Input Capacitance, C

I

-3-pF

DIGITAL OUTPUTS

Output Low (Sink) Current VO = 0.4V 4 10 - mA
Output High (Source) Current VO = 4.5V -4 -6 - mA
Three-State Output Off-State Leakage Current, I
Output Capacitance, C

O

OZ

- ±0.2 ±5 µA

-4-pF

TIMING CHARACTERISTICS

Auto Balance Time (φ1) 33 -

∞

ns

Sample Time (φ2) Note 4 25 - 500 ns
Aperture Delay -15- ns
Aperture Jitter - 100 - ps
Data Valid Time, t
Data Hold Time, t

D

H

Output Enable Time, t
Output Disable Time, t

EN

DIS

Note 4 - 50 65 ns

Note 4 25 40 - ns

-18- ns

-18- ns

POWER SUPPLY CHARACTERISTICS

Device Current (IDD + IA) (Excludes I

) Continuous Conversion (Note 4) - 30 60 mA

REF

Auto Balance (φ1) - 30 60 mA

NOTES:

1. A full scale sine wav e input of greater than f

/2 or the specified input bandwidth (whichever is less) ma y cause an erroneous code.

CLOCK

The -3dB bandwidth for frequency response purposes is greater than 30MHz.

2. VIN (Full Scale) or V

3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1V

+ should not exceed VAA+ + 1.5V for accuracy.

REF

minimum source.

P-P

4. Parameter not tested, but guaranteed by design or characterization.

Timing Waveforms

COMPARATOR DATA IS LATCHED

CLOCK (PIN 18)

IF PHASE (PIN 19)

IS LOW

CLOCK IF

PHASE IS HIGH

DECODED DATA IS SHIFTED
TO OUTPUT REGISTERS

φ2

SAMPLE

N

DAT A

N - 2

AUTO

BALANCE

φ2 φ1φ1 φ2

SAMPLE

N + 1

DAT A

N - 1

FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM

4-12

AUTO

BALANCE

t

H

SAMPLE

N + 2

t

D

DAT A

N