Intersil Corporation CA3306C, CA3306A, CA3306 Datasheet

August 1997

CA3306, CA3306A,

CA3306C

6-Bit, 15 MSPS,

Flash A/D Converters

Features

• CMOS Low Power with Video Speed (Typ) . . . . .70mW

• Parallel Conversion Technique

• Signal Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V

• 15MHz Sampling Rate with Single 5V Supply

• 6-Bit Latched Three-State Output with Overflow Bit

• Pin-for-Pin Retrofit for the CA3300

Applications

• TV Video Digitizing

• Ultrasound Signature Analysis

• Transient Signal Analysis

• High Energy Physics Research

• High Speed Oscilloscope Storage/Display

• General Purpose Hybrid ADCs

• Optical Character Recognition

• Radar Pulse Analysis

• Motion Signature Analysis

• Robot Vision

Description

The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.

The CA3306 family operates over a wide, full scale signal input volt­age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer­ing improved linearity at a lower reference voltage and high operat­ing speed with a 5V supply.

The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos­sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).

Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi­tional comparator is required for the overflow bit.

Ordering Information

PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE (oC) PACKAGE PKG. NO.

CA3306E ±0.5 LSB 15MHz (67ns) -40 to 85 18 Ld PDIP E18.3
CA3306CE ±0.5 LSB 10MHz (100ns) -40 to 85 18 Ld PDIP E18.3
CA3306M ±0.5 LSB 15MHz (67ns) -40 to 85 20 Ld SOIC M20.3
CA3306CM ±0.5 LSB 10MHz (100ns) -40 to 85 20 Ld SOIC M20.3
CA3306D ±0.5 LSB 15MHz (67ns) -55 to 125 18 Ld SBDIP D18.3
CA3306CD ±0.5 LSB 10MHz (100ns) -55 to 125 18 Ld SBDIP D18.3
CA3306J3 ±0.5 LSB 15MHz (67ns) -55 to 125 20 Ld CLCC J20.B
CA3306J3 ±0.5 LSB 10MHz (100ns) -55 to 125 20 Ld CLCC J20.B

Pinouts

CA3306 (PDIP, SBDIP)

TOP VIEW

(MSB) B6

OVERFLO W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

V

SS

V
CE2
CE2

CLK

PHASE

V

REF

1
2
3
4

Z

5
6
7
8
9

+

B5

18

B4

17

REF

16

CENTER
B3

15

B2

14

B1 (LSB)

13
12

V

DD

11

V

IN

V

-

10

REF

| Copyright © Intersil Corporation 1999

(MSB) B6

OVERFLO W

V

SS

NC

V
CE2
CE1

CLK

PHASE

V

REF

CA3306 (SOIC)

TOP VIEW

1
2
3
4
5

Z

6
7
8
9

+

10

4-8

B5

20

B4

19

REF

18

CENTER
B3

17

B2

16

B1 (LSB)

15

V

14

NC

13
12

V
V

11

DD

IN
REF

CA3306 (CLCC)

TOP VIEW

FLOW

OVER-

3212019

V

4

SS

V

5

Z

6

NC

7

CE2
CE1

8

9101112

-

CLK

B5

(MSB)

B6

NC

-

+

REF

V

V

PHASE

File Number

REF

B4

REF

18

CENTER

17

B3

16

B2

15

B1 (LSB)

14

V

DD

13

IN

V

3102.1

Functional Block Diagram

V

IN

φ1

R/2

V

REF

+

R

φ2

CA3306, CA3306A, CA3306C

φ1 φ1

COMP

64

φ2

DQ
CL

THREE-STATE

OVERFLO W

REF

CENTER

V

REF

CLOCK

PHASE

ZENER

DIODE

R

R

≅

120Ω

R

R

R

-

R/2

≅

50kΩ

6.2V NOMINAL

COMP

63

COMP

32

COMP

2

COMP

1

COMP ARATOR

LATCHES

AND

ENCODER

LOGIC

DQ
CL

DQ
CL

DQ
CL

DQ
CL

DQ
CL

DQ
CL

B6 (MSB)

B5

B4

B3

B2

B1 (LSB)

CE1

φ2 (SAMPLE UNKNOWN)

φ1 (AUTO BALANCE)

V

V

SS

V

DD

SS

CE2

Typical Application Circuit

+12V

+12V

5kΩ

+

-

CA741CE

560Ω

CLOCK

6.2V

0.1µF

+5V

OF

B6

1

2

3

4

5

6

7

8

9

OF

V

SS

V

Z

CE2

CE1

CLK

PH

V

REF+

CA3306

V

B5

B4

RC

B3

B2

B1

V

DD

V

REF-

18

17

0.1µF

16

15

14

13

12

11

IN

10

B6
B5
B4

B3
B2
B1

(LSB)

0.2µF

SIGNAL
INPUT

DAT A
OUTPUT

+5V

10µF

4-9

CA3306, CA3306A, CA3306C

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, V

Voltage Referenced to VSS Terminal . . . . . . . . . . . -0.5V to +8.5V

Input Voltage Range

All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V

DC Input Current

CLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

DD

Operating Conditions

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V

Temperature Range (TA)

Ceramic Package (D Suffix) . . . . . . . . . . . . . . . . . -55oC to 125oC

Plastic Package (E or M Suffix). . . . . . . . . . . . . . . .-40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

SBDIP Package. . . . . . . . . . . . . . . . . . . . 75 24

PDIP Package. . . . . . . . . . . . . . . . . . . . . 95 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . . . 115 N/A

CLCC Package . . . . . . . . . . . . . . . . . . . . 80 28

Maximum Junction Temperature

Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 6 - - Bits
Integral Linearity Error, INL CA3306, CA3306C - ±0.25 ±0.5 LSB

Differential Linearity Error,
DNL

Offset Error (Unadjusted) CA3306, CA3306C (Note 1) - ±0.5 ±1 LSB

Gain Error (Unadjusted) CA3306, CA3306C (Note 2) - ±0.5 ±1 LSB

Gain Temperature Coefficient - +0.1 - mV/
Offset Temperature Coefficient - -0.1 - mV/oC
DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale)
Maximum Conversion Speed CA3306C 10 13 - MSPS

Maximum Conversion Speed CA3306C (Note 4)

Allowable Input Bandwidth (Note 4) DC - f

-3dB Input Bandwidth - 30 - MHz
Signal to Noise Ratio, SNR fS = 15MHz, fIN = 100kHz - 34.6 - dB

RMSSignal

--------------------------------

=

RMSNoise

= 25oC, VDD = 5V, V

A

CA3306A, 10MHz for CA3306C

CA3306A - ±0.2 ±0.25 LSB
CA3306, CA3306C - ±0.25 ±0.5 LSB
CA3306A - ±0.2 ±0.25 LSB

CA3306A - ±0.25 ±0.5 LSB

CA3306A - ±0.25 ±0.5 LSB

CA3306, CA3306A 15 20 - MSPS

CA3306, CA3306A 18 - - MSPS

φ1, φ2 ≥ Minimum

fS = 15MHz, fIN = 5MHz - 33.4 - dB

+ = 4.8V, VSS = V

REF

- = GND, Cloc k = 15MHz Square Wave for CA3306 or

REF

12 - - MSPS

CLOCK/2

MHz

o

C

Signal to Noise Ratio, SINAD fS = 15MHz, fIN = 100kHz - 34.2 - dB

RMSSignal

------------------------------------------------------------

=

RMSNoise+Distortion

Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - -46.0 - dBc

Effective Number of Bits, ENOB fS = 15MHz, fIN = 100kHz - 5.5 - Bits

fS = 15MHz, fIN = 5MHz - 29.0 - dB

fS = 15MHz, fIN = 5MHz - -30.0 - dBc

fS = 15MHz, fIN = 5MHz - 4.5 - Bits

4-10

CA3306, CA3306A, CA3306C

Electrical Specifications T

= 25oC, VDD = 5V, V

A

+ = 4.8V, VSS = V

REF

- = GND, Cloc k = 15MHz Square Wave for CA3306 or

REF

CA3306A, 10MHz for CA3306C (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ANALOG INPUTS

Positive Full Scale Input Range (Notes 3, 4) 1 4.8 VDD + 0.5 V
Negative Full Scale Input Range (Notes 3, 4) -0.5 0 VDD - 1 V
Input Capacitance -15- pF
Input Current VIN = 4.92V, VDD = 5V - - ±500 µA

INTERNAL VOLTAGE REFERENCE

Zener Voltage IZ = 10mA 5.4 6.2 7.4 V
Zener Dynamic Impedance IZ = 10mA, 20mA - 12 25 Ω
Zener Temperature Coefficient - -0.5 - mV/oC

REFERENCE INPUTS

Resistor Ladder Impedance 650 1100 1550 Ω

DIGITAL INPUTS

Maximum VIN, Logic 0 All Digital Inputs (Note 4) - - 0.3 x V
Maximum VIN, Logic 1 All Digital Inputs (Note 4) 0.7 x V

DD

-- V

DD

V

Digital Input Current Except CLK, VIN = 0V, 5V - ±1 ±5 µA
Digital Input Current CLK Only - ±100 ±200 µA

DIGITAL OUTPUTS

Digital Output Three-State Leakage V
Digital Output Source Current V
Digital Output Sink Current V

= 0V, 5V - ±1 ±5 µA

OUT

= 4.6V -1.6 - - mA

OUT

= 0.4V 3.2 - - mA

OUT

TIMING CHARACTERISTICS

Auto Balance Time (φ1) CA3306C 50 -

∞

ns

CA3306, CA3306A 33 - ∞

Sample Time (φ2) CA3306C (Note 4) 33 - 5000 ns

CA3306, CA3306A 22 - 5000 ns
Aperture Delay -8- ns
Aperture Jitter - 100 - ps

P-P

Output Data Valid Delay, tDCA3306C - 35 50 ns

CA3306, CA3306A - 30 40 ns
Output Data Hold Time, t
Output Enable Time, t
Output Disable Time, t

EN

DIS

H

(Note 4) 15 25 - ns

-20- ns

-15- ns

POWER SUPPLY CHARACTERISTICS

IDD Current, Refer to Figure 4 CA3306C Continuous Conversion (Note 4) - 11 20 mA

CA3306, CA3306A - 14 25 mA
IDD Current Continuous φ1 - 7.5 15 mA

NOTES:

1. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (V

2. GAIN ERROR is the difference the input voltage that causes the 3F16 to overflow output code transition and (V

3. The total input voltage range, set by V

REF

+ and V

-, may be in the range of 1 to (VDD + 1) V.

REF

REF

REF

+ - V

+ - V

REF

-) x 127/128.

REF

-)/128.

4. Parameter not tested, but guaranteed by design or characterization.

4-11

Timing Waveforms

COMPARATOR DATA IS LATCHED DECODED DATA IS SHIFTED TO OUTPUT REGISTERS

CA3306, CA3306A, CA3306C

CLOCK IF

PHASE IS HIGH

CLOCK IF

PHASE IS LOW

CE1

CE2

BITS 1-6

φ2 φ2 φ2φ1φ1

DAT A

N - 2

t

DIS

AUTO

BALANCE

DAT A

N - 1

SAMPLE

t

H

FIGURE 1. INPUT-TO-OUTPUT

t

EN

HIGH

IMPEDANCE

N + 1

AUTO

BALANCE

t

D

t

DIS

HIGH

IMPEDANCE

DAT A

N

t

DIS

SAMPLE

N + 2

DAT ADAT ADAT A

CLOCK

OUTPUT

SAMPLE ENDS

φ2

OLD DATA

OF

FIGURE 3A.

CLOCK

OUTPUT

φ1

t

D

φ2

OLD DATA

DAT A

FIGURE 2. OUTPUT ENABLE

φ2

NEW DATA

CLOCK

OUTPUT

SAMPLE ENDS

FIGURE 3C.

FIGURE 3. PULSE MODE

IMPEDANCE

SAMPLE ENDS

OLD

DAT A

INVALID

DAT A

HIGH

DAT A

φ2 φ1φ1φ2φ1

t

D

OLD

DATA +1

FIGURE 3B.

NEW
DAT A

φ2φ1φ2φ1

t

D

NEW

DAT A

4-12