Intersil Corporation CA3130A, CA3130 Datasheet

CA3130, CA3130A

Data Sheet September 1998 File Number 817.4

15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output

CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance.TheuseofPMOStransistors in the input stage
results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important
attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.

The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.

The CA3130A offers superior input characteristics over
those of the CA3130.

Pinouts

CA3130, CA3130A

(PDIP, SOIC)

TOP VIEW

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5 TΩ (1.5 x 1012Ω) (Typ)

I

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

I

. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)

• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

OFFSET

NON-INV.

PHASE
COMPENSATION

OFFSET

INPUT

NON-INV.

1

NULL

INV.

2

INPUT

3

INPUT

4

V-

CA3130, CA3130A

1

NULL

2

INV.

3

INPUT

(METAL CAN)

-

+

TOP VIEW

TAB

8

-

+

4
V- AND CASE

1

8

STROBE

7

V+

6

OUTPUT

5

OFFSET
NULL

STROBE

+

7

V

6

OUTPUT

OFFSET

5

NULL

Ordering Information

TEMP.

PART NO.

(BRAND)

CA3130AE -55 to 125 8 Ld PDIP E8.3
CA3130AM

(3130A)

CA3130AM96

(3130A)

CA3130AT -55 to 125 8 Pin Metal Can T8.C
CA3130E -55 to 125 8 Ld PDIP E8.3
CA3130M

(3130)

CA3130M96

(3130)

CA3130T -55 to 125

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

RANGE

(oC) PACKAGE

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC
Tape and Reel

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC
Tape and Reel

8 Pin Metal Can

| Copyright © Intersil Corporation 1999

PKG.

NO.

M8.15

M8.15

T8.C

CA3130, CA3130A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input-Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Metal Can Package . . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage |VIO|VS = ±7.5V - 8 15 - 2 5 mV
Input Offset Voltage

Temperature Drift
Input Offset Current |IIO|VS = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current I
Large-Signal Voltage Gain A

Common-Mode
Rejection Ratio

Common-Mode Input
Voltage Range

Power-Supply
Rejection Ratio

Maximum Output Voltage VOM+RL = 2kΩ 12 13.3 - 12 13.3 - V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA

Supply Current I+ VO = 7.5V,

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

TEST

CONDITIONS

∆VIO/∆T - 10 - - 10 - µV/oC

I

OL

CMRR 70 90 - 80 90 - dB

V

ICR

∆VIO/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V

VOM-RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

VOM+RL = ∞ 14.99 15 - 14.99 15 - V

VOM-RL = ∞ - 0 0.01 - 0 0.01 V

IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA

I+ VO = 0V,

VS = ±7.5V - 5 50 - 5 30 pA
VO = 10V

RL = 2kΩ

RL = ∞

RL = ∞

P-P

50 320 - 50 320 - kV/V
94 110 - 94 110 - dB

CA3130 CA3130A

UNITSMIN TYP MAX MIN TYP MAX

0 -0.5 to 12 10 0 -0.5 to 12 10 V

- 10 15 - 10 15 mA

-23-23mA

2

CA3130, CA3130A

Electrical Specifications Typical Values Intended Only for Design Guidance, V

Unless Otherwise Specified

SUPPLY

= ±7.5V, TA = 25oC

CA3130,

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4and 5 or

CA3130A UNITS

±22 mV

4 and 1
Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e

I
I

N

f = 1MHz 4.3 pF

BW = 0.2MHz, RS = 1MΩ

1.5 TΩ

23 µV

(Note 3)
Open Loop Unity Gain Crossover Frequency

(For Unity Gain Stability ≥47pF Required.)

f

T

CC = 0 15 MHz

CC = 47pF 4 MHz
Slew Rate: SR

CC = 0 30 V/µsOpen Loop

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,

r

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4V

)t

P-P

S

RL = 2kΩ

(Voltage Follower)

CL = 25pF,

0.09 µsRise Time t

1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T

= 25oC

A

Unless Otherwise Specified (Note 4)

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage V
Input Offset Current I
Input Current I

IO

IO

I

82mV

0.1 0.1 pA
22pA

Common-Mode Rejection Ratio CMRR 80 90 dB
Large-Signal Voltage Gain A

OL

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

ICR

0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25oC.

3

Schematic Diagram

CA3130, CA3130A

BIAS CIRCUIT

Z

1

8.3V

R

1

40kΩ

R

2

5kΩ

NON-INV.

INPUT

3

+

INV.-INPUT

2

-

Q

D

1

D

2

D

3

D

4

1

INPUT STAGE

D5D

CURRENT SOURCE FOR

Q6AND Q

Q

2

Q

4

6

Q

6

R

3

1kΩ

Q

(NOTE 5)

Q

10

9

7

D7D

Q

7

R

4

1kΩ

“CURRENT SOURCE

LOAD” FOR Q

Q

3

Q

5

SECOND
STAGE

8

Q

11

11

OUTPUT
STAGE

Q

Q

V+

7

8

OUTPUT

6

12

R

5

1kΩ

5

R

6

1kΩ

OFFSET NULL

1 8 4

NOTE:

5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the
output stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentiallyrises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the

COMPENSATION STROBING

V-

ohmic load resistance presented tothe amplifier isvery high
(e.g.,when the amplifier output is used todrive CMOS digital
circuits in Comparator applications).

Input Stage

The circuit of the CA3130is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
transistors (Q
with resistors R
function as a differential-to-single-ended conv erter to provide
base drive to the second-stage bipolar transistor (Q
nulling, when desired, can be effected by connecting a
100,000Ω potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade-connected
PMOS transistors Q
the input stage. The biasing circuit for the constant-current
source is subsequently described. The small diodes D

, Q7) working into a mirror-pair of bipolar

6

, Q10) functioning as load resistors together

9

through R6. The mirror-pair transistors also

3

11

, Q4 are the constant-current source for

2

). Offset

5

4

CA3130, CA3130A

through D8provide gate-oxide protection against high-voltage
transients, including static electricity during handling for Q

6

and Q7.

CA3130

+

3

INPUT

2

200µA 200µA

AV≈ 5X

1.35mA

BIAS CKT.

AV≈

6000X

8mA
(NOTE 5)
0mA
(NOTE 7)

≈

A

V

30X

-

C

C

COMPENSATION

OFFSET

NULL

NOTES:

6. Totalsupplyvoltage(forindicatedvoltagegains)=15Vwithinput
terminals biased so that Terminal 6 potential is +7.5V above Ter­minal 4.

7. Total supply voltage (for indicated voltage gains) = 15V with out­put terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

(WHEN REQUIRED)

STROBE

815

V+

7

OUTPUT

6

V-

4

Second-Stage

Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q

11

and its cascade-connected load resistance provided by
PMOS transistors Q

and Q5. The source of bias potentials

3

forthese PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat abo ve 8.3V, resistor R
and zener diode Z1serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
D

through D4, and PMOS transistor Q1. A tap at the junction

1

of resistor R
about 4.5V for PMOS transistors Q

and diode D4 provides a gate-bias potential of

1

and Q5 with respect to

4

Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
7 to provide gate bias for PMOS transistors Q
should be noted that Q
both Q

and Q3. Since transistors Q1,Q2,Q3are designed to

2

is “mirror-connected (see Note 8)” to

1

with respect to Terminal

1

and Q3. It

2

be identical, the approximately 200µA current in Q
establishes a similar current in Q2and Q3as constant current
sources for both the first and second amplifier stages,
respectively.

, diodes

1

1

2

At total supply voltages somewhat less than 8.3V, zener
diode Z
developed across series-connected R

becomes nonconductive and the potential,

1

, D1-D4, and Q1,

1

varies directly with variations in supply voltage.
Consequently, the gate bias for Q

and Q2,Q3varies in

4,Q5

accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier,its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large­signal excursionsare non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve

0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transis­tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.

17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V

T

= 25oC

A

15

12.5

10

500Ω

7.5

5

2.5

0

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF

LOAD RESISTANCE = 5kΩ

2kΩ

1kΩ

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

CMOS OUTPUT STAGE

17.5 2012.5 15107.52.5 50

22.5

Input Current Variation with Common Mode Input
Voltage

As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T

= 25oC when Terminals 2 and 3 are at a common-mode

A

potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T

=25oC.

A

5