intersil CA3130, CA3130A DATA SHEET

CA3130, CA3130A

Data Sheet August 1, 2005 FN817.6

15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

CA3130A and CA3130 are op amps that combine the advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS transistors in the input stage results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit.

The CA3130 Series circuits operate at supply voltages ranging from 5V to 16V, (±2.5V to ±8V). They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage.

• The CA3130A offers superior input characteristics over those of the CA3130.

Ordering Information

PART NO.

(BRAND)

CA3130AE CA3130AM

(3130A)

CA3130AM96

(3130A)

CA3130AMZ

(3130AZ) (Note)

CA3130AMZ96

(3130AZ) (Note)

CA3130E CA3130EZ

(Note) CA3130M

(3130)

CA3130M96

(3130)

CA3130MZ

(3130MZ) (Note)

CA3130MZ96

(3130MZ)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TEMP.

RANGE (

C) PACKAGE

-55 to 125 8 Ld PDIP E8.3

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

-55 to 125 8 Ld PDIP E8.3

-55 to 125 8 Ld PDIP* (Pb-free)

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

DWG. #

M8.15

E8.3

M8.15

PKG.

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5 TΩ (1.5 x 1012Ω) (Typ)

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

. . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators (Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• Voltage Followers (e.g. Follower for Single-Supply D/A Converter)

• Voltage Regulators (Permits Control of Output Voltage Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

Pinout

CA3130, CA3130A

(PDIP, SOIC)

TOP VIEW

OFFSET

NON-INV.

NULL

INV.

INPUT INPUT

1 2

3 4

V-

8 7 6 5

STROBE V+ OUTPUT OFFSET

NULL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

CA3130, CA3130A

Absolute Maximum Ratings

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+

+8V) to (V- -0.5V)

Input-Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -50

C to 125oC

Thermal Information

Thermal Resistance (Typical, Note 2) θ

PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder process-

(oC/W) θJC (oC/W)

C to 150oC

ing only. They are not intended for use in Reflow solder processing applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply. is measured with the component mounted on an evaluation PC board in free air.

2. θ

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage |V Input Offset Voltage

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

TEST

CA3130 CA3130A

CONDITIONS

|VS = ±7.5V - 8 15 - 2 5 mV

∆V

/∆T - 10 - - 10 - µV/oC

UNITSMIN TYP MAX MIN TYP MAX

Temperature Drift Input Offset Current |I Input Current I Large-Signal Voltage Gain A

Common-Mode

|VS = ±7.5V - 0.5 30 - 0.5 20 pA

VS = ±7.5V - 5 50 - 5 30 pA VO = 10V

RL = 2kΩ

P-P

50 320 - 50 320 - kV/V 94 110 - 94 110 - dB

CMRR 70 90 - 80 90 - dB

Rejection Ratio Common-Mode Input

Voltage Range Power-Supply

Rejection Ratio Maximum Output Voltage V

Maximum Output Current I

Supply Current I+ V

ICR

/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V

∆V

+RL = 2kΩ 12 13.3 - 12 13.3 - V

-RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

+RL = ∞ 14.99 15 - 14.99 15 - V

-RL = ∞ - 0 0.01 - 0 0.01 V

+ (Source) at VO = 0V 12 22 45 12 22 45 mA

- (Sink) at VO = 15V 12 20 45 12 20 45 mA

= 7.5V,

= ∞

I+ V

= 0V, = ∞

0 -0.5 to 12 10 0 -0.5 to 12 10 V

- 10 15 - 10 15 mA

-23-23mA

CA3130, CA3130A

Electrical Specifications Typical Values Intended Only for Design Guidance, V

Unless Otherwise Specified

= ±7.5V, TA = 25oC

SUPPLY

CA3130,

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or

CA3130A UNITS

±22 mV

4 and 1 Input Resistance R Input Capacitance C Equivalent Input Noise Voltage e

Open Loop Unity Gain Crossover Frequency (For Unity Gain Stability ≥47pF Required.)

I I

f = 1MHz 4.3 pF

BW = 0.2MHz, RS = 1MΩ

(Note 3)

CC = 0 15 MHz

= 47pF 4 MHz

1.5 TΩ

23 µV

Slew Rate: SR

= 0 30 V/µsOpen Loop

Closed Loop C

= 56pF 10 V/µs

Transient Response: CC = 56pF,

= 25pF,

Overshoot OS 10 %

Settling Time (To <0.1%, V

= 4V

P-P

= 2kΩ

(Voltage Follower)

0.09 µsRise Time t

1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of R

up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T

Unless Otherwise Specified (Note 4)

= 25oC

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage V Input Offset Current I Input Current I

82mV

0.1 0.1 pA 22pA

Common-Mode Rejection Ratio CMRR 80 90 dB Large-Signal Voltage Gain A

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

ICR

Supply Current I+ V

Power Supply Rejection Ratio ∆V

/∆V+ 200 200 µV/V

= 5V, RL = ∞ 300 300 µA

= 2.5V, RL = ∞ 500 500 µA

0 to 2.8 0 to 2.8 V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25

Schematic Diagram

1 8 4

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 1, provide the total gain of the CA3130. A biasing circuit provides two potentials for common use in the first and second stages.

Terminal 8 can be used both for phase compensation and to strobe the output stage into qui esce nce . When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply-rail potential at Terminal 7. This condition of essentially zero current drain in

the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g.,when the amplifier output is used to drive CMOS digital circuits in Comparator applications).

Input Stage

The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q transistors (Q with resistors R

The mirror-pair transistors also function as a differential -tosingle-ended converter to provide base driv e to the se con dstage bipolar transistor (Q can be effected by connecting a 100,00 0Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4.

, Q7) working into a mirror-pair of bipolar

, Q10) functioning as load resistors together

through R6.

). Offset nulling, when desired,

CA3130, CA3130A

CA3130

INPUT

200µA 200µA

AV ≈ 5X

1.35mA

BIAS CKT.

AV ≈

6000X

8mA (NOTE 5) 0mA (NOTE 7)

≈

30X

COMPENSATION

OFFSET

NULL

NOTES:

6. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4.

7. T otal supply v oltage (f or indicated voltage gains) = 15V with output terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

(WHEN REQUIRED)

815

STROBE

V+

OUTPUT

V-

Cascade-connected PMOS transistors Q2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described.

The small diodes D

through D8 provide gate-oxide protection

against high-voltage transients , incl uding static ele ctricity during handling for Q

and Q7.

Second-Stage

Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q

and its cascade-connected load resistance provided by PMOS transistors Q

and Q5. The source of bias potentials

for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, some w hat above 8.3V, resistor R2 and zener diode Z the series-connected circuit, consisting of resistor R D

through D4, and PMOS transistor Q1. A tap at the junction

of resistor R about 4.5V for PMOS transistors Q Terminal 7. A potential of about 2.2V is developed across diode-connected PMOS transistor Q 7 to provide gate bias for PMOS transistors Q should be noted that Q both Q

and Q3. Since transistors Q1, Q2, Q3 are designed to

be identical, the approximately 200µA current in Q establishes a similar curr ent in Q

serve to establish a voltage of 8.3V across

and diode D4 provides a gate-bias potential of

is “mirror-connected (see Note 8)” to

and Q5 with respect to

with respect to T erminal

and Q3 as constant current

, diodes

and Q3. It

sources for both the first and second amplifier stages, respectively.

At total supply voltages somewhat less than 8.3V, zener diode Z developed across series-connected R

becomes nonconductive and the potential,

, D1-D4, and Q1,

varies directly with variations in supply voltage. Consequently, the gate bias for Q

, Q5 and Q2, Q3 varies in

accordance with supply-voltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 2. Typical op amp loads are readily driven by the output stage. Because largesignal excursions are non-linear, requiring feedback f or good waveform reproduction, transient delays may be encountered. As a voltage follower , the amplifier can achiev e

0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transistor-pairs in linear-circuit applications, see File Number 619, data sheet on CA3600E “CMOS Transistor Array”.

17.5 SUPPLY VOLTAGE: V+ = 15, V- = 0V

= 25oC

12.5

500Ω

7.5

2.5

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 2. VOL TAGE TRANSFER CHARACTERISTICS OF

LOAD RESISTANCE = 5kΩ

2kΩ

1kΩ

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

CMOS OUTPUT STAGE

17.5 2012.5 15107.52.5 50

22.5

CA3130, CA3130A

Input Current Variation with Common Mode Input Voltage

As shown in the Table of Electrical Specifications, the input current for the CA3130 Series Op Amps is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common-mode potential of +7.5V with respect to negative supply T erminal 4. Figure 3 contains data showing the variation of input current as a function of common-mode input voltage at TA = 25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate-protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to Terminal 4 potential, and the Metal Can case of the CA3130 is also internally tied to T erminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents.

TA = 25oC

7.5

INPUT VOLTAGE (V)

2.5

-101234567

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

INPUT CURRENT (pA)

CA3130

V+

15V

-10V

V-

Offset Nulling

Offset-voltage nulling is usually accomplished with a 100,000Ω potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset-null adjustment usually can be effected with the slider arm positioned in the mid-point of the potentiometer’s total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate-protective diodes in the input circuit. As with any semiconductor-junction device, including op amps with a junction-FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 4 provides data on the

typical variation of input bias current as a function of temperature in the CA3130.

4000

VS = ±7.5V

1000

100

INPUT CURRENT (pA)

-80 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

In applications requiring the lowest practical input current and incremental increases in current because of “warm-up” effects, it is suggested that an appropriate heat sink be used with the CA3130. In addition, when “sinking” or “sourcing” significant output current the chip temperature increases, causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input current variations.

Input Offset Voltage (VIO) Variation with DC Bias and Device Operating Life

It is well known that the characteristics of a MOSFET device can change slightly when a DC gate-source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA3130 should be alert to the possible impacts of this effect if the application of the device involves e xtended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 5 shows typical data pertinent to shifts in offset voltage encountered with CA3130 devices (metal can package) during life testing. At lower temperatures (metal can and plastic), for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2VDC differential voltage example represents conditions when the amplifier output stage is “toggled”, e.g., as in comparator applications.

CA3130, CA3130A

DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V

OUTPUT STAGE TO GGLED

OFFSET VOLTAGE SHIFT (mV)

0 500 1000 1500 2000 2500 3000 3500 4000

FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE

FIGURE 6A. DUAL POWER SUPPLY OPERATION

FIGURE 6B. SINGLE POWER SUPPLY OPERATION

FIGURE 6. CA3130 OUTPUT STA GE IN DU AL AND SINGLE

DIFFERENTIAL DC VOLT AGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2

SHIFT vs OPERATING LIFE

CA3130

POWER SUPPLY OPERATION

TA = 125oC FOR TO-5 PACKAGES

TIME (HOURS)

V+

V-

V+

increased and current flow through Q

(from the positive

supply) decreases correspondingly. When the gate terminals of Q

and Q12 are driven increasingly negative with respect

to ground, current flow through Q flow through Q

is decreased accordingly.

is increased and current

Single-supply Operation: Initially, let it be assumed that the value of R

is very high (or disconnected), and that the input-

terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2, i.e ., the voltage drops across Q

and Q12 are of equal magnitude. Figure 20 shows

typical quiescent supply-current vs supply-voltage for the CA3130 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply-current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage-transfer char acteristics (see Figure 2). If either Q

or Q12 are swung out of their linear regions tow ard cut-off

(a non-linear region), there will be a corresponding reduction in supply-current. In the extreme case, e.g., with Terminal 8 swung down to ground poten tial (or tied to groun d), NMOS transistor Q series-connected transistors Q

is completely cut off and the supply-current to

, Q12 goes essentially to zero.

The two preceding stages in the CA3130, however, continue to draw modest supply-current (see the lowe r curve in Figure

20) even though the outp ut stage is stro bed off. Figure 6A shows a dual-supply arrangement for the output stage that can also be strobed off, assuming R

= ∞ by pulling the

potential of Terminal 8 down to that of Terminal 4. Let it now be assumed that a load-resistance of nominal

value (e.g., 2kΩ) is connected between Terminal 6 and ground in the circuit of Figure 6B. Let it be assumed again that the input-terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q and transistor Q

must now supply quiescent current to both RL

, it should be apparent that under these

conditions the supply-current must increase as an inverse function of the R drop across PMOS transistor Q

magnitude. Figure 22 shows the voltage-

as a function of load

current at several supply voltages. Figure 2 shows the voltage-transfer characteristics of the output stage for several values of load resistance.

Power-Supply Considerations

Because the CA3130 is very useful in single-supply applications, it is pertinent to review some considerations relating to power-supply current consumption under both single-and dual-supply service. Figures 6A and 6B show the CA3130 connected for both dual-and single-supply operation.

Dual-supply Operation: When the output voltage at Terminal 6 is 0V, the currents supplied by the two power supplies are equal. When the gate terminals of Q increasingly positive with respect to ground, current flow through Q

(from the negative supply) to the load is

and Q12 are driven

Wideband Noise

From the standpoint of low-noise performance considerations, the use of the CA3130 is most advantageous in applications where in the source resistance of the input signal is on the order of 1MΩ or more. In this case, the total input-referred noise voltage is typically only 23µV when the test-circuit amplifier of Figure 7 is operated at a total supply voltage of 15V. This value of total input-referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for

CA3130, CA3130A

values of source resistance very much greater than 1MΩ, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors.

+7.5V

0.01µF

0.01 µF

30.1kΩ

1kΩ

NOISE

VOLTAGE

OUTPUT

1MΩ

BW (-3dB) = 200kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 23µV (TYP)

FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED

FOR WIDEBAND NOISE MEASUREMENTS

47pF -7.5V

Typical Applications

Voltage Followers

Operational amplifiers with very high input resistances, like the CA3130, are particularly suited to service as voltage followers. Figure 8 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA3130 in a split-supply configuration.

A voltage follower , operated from a single supply, is shown in Figure 9, together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 9A with input-signal ramping. The wavef orms in Figure 9B show that the follower does not lose its input-to-output phase-sense, even though the input is being swung 7.5V below ground potential. This unique cha racteristic is an important attribute in both operational amplifier and comparator applications. Figure 9B also shows the manner in which the CMOS output stage permits the output signal to swing down to the negative supply-rail potential (i.e., ground in the case shown). The digital-to-analog converter (DAC) circuit, described later, illustrates the practical use of the CA3130 in a single-supply voltage-follower application.

9-Bit CMOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) is shown in Figure 10. This system combines the concepts of multiple-switch CMOS lCs, a low-cost ladder network of discrete metal-oxide-film resistors, a CA3130 op amp connected as a follower, and an inexpensive monolithic regulator in a simple single power-supply arrangement. An additional feature of the DAC is that it is readily interfaced

with CMOS input logic, e.g., 10V logic levels are used in the circuit of Figure 10.

The circuit uses an R/2R voltage-ladder network, with the output potential obtained directly by terminating the ladder arms at either the positive or the negative power-supply terminal. Each CD4007A contains three “inverters”, each “inverter” functioning as a single-pole double-throw s witch to terminate an arm of the R/2R network at either the positive or negative power-supply terminal. The resistor ladder is an assembly of 1% tolerance metal-oxide film resistors. The five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000Ω resistors from the same manufacturing lot.

A single 15V supply provides a positive bus for the CA3130 follower amplifier and feeds the CA3085 vo ltage regulator. A “scale-adjust” function is provided by the regulator output control, set to a nominal 10V level in this system. The linevoltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in the supply. The flexibility afforded by the CMOS building blocks simplifies the design of DAC systems tailored to particular needs.

Single-Supply, Absolute-Value, Ideal Full-Wave Rectifier

The absolute-value circuit using the CA3130 is shown in Figure 11. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative-going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative-going excursion of the input signal, the CA3130 functions as a normal inverting amplifier with a gain equal to -R

. When the equality of the two equations

2/R1

shown in Figure 11 is satisfied, the full-wave output is symmetrical.

Peak Detectors

Peak-detector circuits are easily implemented with the CA3130, as illustrated in Figure 12 for both the peak-positive and the peak-negative circuit. It should be noted that with large-signal inputs, the bandwidth of the peak-negative circuit is much less than that of the peak-positive circuit. The second stage of the CA3130 limits the bandwidth in this case. Negative-going output-signal excursion requires a positive-going signal excursion at the collector of transistor Q

, which is loaded by the intrinsic capacitance of the

associated circuitry in this mode. On the other hand, during a negative-going signal excursion at the collector of Q transistor functions in an active “pull-down” mode so that the intrinsic capacitance can be discharged more expeditiously.

, the

CA3130, CA3130A

10kΩ

BW (-3dB) = 4MHz

SR = 10V/µs

= 56pF

-7.5V

2kΩ

0.1µF

+7.5V

0.01µF

25pF

2kΩ

10kΩ

56pF

+15V

0.01µF

2kΩ

100kΩ

OFFSET

ADJUST

0.1µF

Top Trace: Output

Center Trace: Input

FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,

200ns/DIV.)

Top Trace: Output Signal; 2V/Div., 5µs/Div.

Center Trace: Difference Signal; 5mV/Div., 5µs/Div.

Bottom Trace: Input Signal; 2V/Div., 5µs/Div.

FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)

FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS

FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL

RAMPING (2V/DIV., 500µs/DIV.)

Top Trace: Output; 5V/Div., 200µs/Div.

Bottom Trace: Input Signal; 5V/Div., 200µs/Div.

FIGURE 9B. OUTPUT WAVEFORM WITH GROUND

REFERENCE SINE-WAVE INPUT

FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS. (E.G., FOR USE IN SINGLE-SUPPL Y D/A CONVER TER; SEE FIGURE 9 IN AN6080)

+10.010V

10V LOGIC INPUTS

LSB

987 654 321

CD4007A

“SWITCHES”

402K1%200K

806K 1%

14 11

CD4007A

“SWITCHES”

12 12

8 5

100K1%806K1%806K

806K

6 3 101036

CD4007A

“SWITCHES”

1313 1 12

(2)

806K1%806K1%806K

MSB

(4)

BIT

6 - 9

1 2 3 4 5

STANDARD

±0.1% ±0.2% ±0.4% ±0.8% ±1% ABS

REQUIRED

RATIO-MATCH

NOTE: All resistances are in ohms.

(8)

+15V

VOLTAGE

REGULATOR

2µF 25V

806K 1%

CA3085

0.001µF

806K1%750K

+10.010V

22.1k

REGULATED

VOLTAGE

3.83k 1%

OUTPUT

LOAD

ADJ

100K

OFFSET

NULL

PARALLELED

RESISTORS

+15V

CA3130

0.1µF

10K

VOLTAGE FOLLOWER

56pF

FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

CA3130, CA3130A

INPUT;

P-P

BW (-3dB) = 1.3MHz

0.3V

INPUT;

P-P

BW (-3dB) = 240kHz

10kΩ

+7.5V

0.01µF

CA3130

2kΩ

-7.5V

1N914

0.01µF

100

kΩ

OUTPUT

+DC

5µF

P-P

BW (-3dB) = 360kHz

0.3V

INPUT;

P-P

BW (-3dB) = 320kHz

10kΩ

CA3130

2kΩ

FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT

FIGURE 12. PEAK-DETECTOR CIRCUITS

CURRENT

LIMIT

3Ω

ADJ

1kΩ

-7.5V

+7.5V

0.01µF

1N914

0.01µF

100

kΩ

OUTPUT

-DC

5µF

+20V

INPUT

390Ω

0.01µF

CA3086

8, 7

CA3086

10 7 3

11 8 1 5

2.2kΩ

1, 2

62kΩ

1kΩ

25µF

4269

5µF 25V

OUTPUT 0 TO 13V

40mA

50kΩ

1kΩ

VOLTAGE ADJUST

IC1

56pF

CA3130

100kΩ

20kΩ

ERROR AMPLIFIER

0.01 µF

30kΩ

REGULATION (NO LOAD TO FULL LOAD): <0.01% INPUT REGULATION: 0.02%/V HUM AND NOISE OUTPUT: <25µV UP TO 100kHz

FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

CA3130, CA3130A

4.3kΩ 1W

100µF

+55V

INPUT

CA3086 10, 11

9 8, 7

2.2kΩ

1, 2

3 5

1kΩ

62kΩ

5µF

REGULATION (NO LOAD TO FULL LOAD): <0.005% INPUT REGULATION: 0.01%/V HUM AND NOISE OUTPUT: <250µV

FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)

UP TO 100kHz

RMS

2N2102

3.3kΩ 1W

50kΩ

2N3055

VOLTAGE ADJUST

2N2102

1Ω

10kΩ

1000pF

CA3130

CURRENT LIMIT ADJUST

2N5294

ERROR AMPLIFIER

43kΩ

10kΩ

8.2kΩ

100µF

OUTPUT:

0.1 TO 50V AT 1A

1kΩ

Error-Amplifier in Regulated-Power Supplies

The CA3130 is an ideal choice for error-amplifier service in regulated power supplies since it can function as an erroramplifier when the regulated output voltage is required to approach zero. Figure 13 shows the schematic diagram of a 40mA power supply capable of providing regulated output voltage by continuous adjustment over the range from 0V to 13V. Q function as zeners to provide supply-voltage for the CA3130 comparator (IC low impedance, temperature-compensated source of adjustable reference voltage for the error amplifier. Transistors Q transistor-array lC) are connected in parallel as the seriespass element. Transistor Q limiting device by diverting base drive from the series-pass transistors, in accordance with the adjustment of resistor R

Figure 14 contains the schematic diagram of a regulated power-supply capable of providing regulated output voltage by continuous adjustment over the range from 0.1V to 50V and currents up to 1A. The error amplifier (lC associated with lC although the output of lC (Q

and Q4 in lC2 (a CA3086 transistor-array lC)

). Q1, Q2, and Q5 in IC2 are configured as a

, Q2, Q3, and Q4 in lC3 (another CA3086

in lC3 functions as a current-

) and circuitry

function as previously described,

is boosted by a discrete transistor

) to provide adequate base drive for the Darlington-

connected series-pass transistors Q

, Q2. Transistor Q3

functions in the previously described current-limiting circuit.

Multivibrators

The exceptionally high input resistance presented by the CA3130 is an attractive feature for m ultivibrator circuit design because it permits the use of timing circuits with high R/C ratios. The circuit diagram of a pulse generator (astable multivibrator), with provisions for independent control of the “on” and “off” periods, is shown in Figure 15. Resistors R and R

are used to bias the CA3130 to the mid-point of the

supply-voltage and R repetition rate is selected by positioning S

is the feedback resistor. The pulse

to the desired

position and the rate remains essentially constant when the resistors which determine “on-period” and “off-period” are adjusted.

Function Generator

Figure 16 contains a schematic diagram of a function generator using the CA3130 in the integrator and threshold detector functions. This circuit generates a triangular or square-wave output that can be swept over a 1,00 0,000:1 range (0.1Hz to 100kHz) by means of a single control, R voltage-control input is also available f or remote sweepcontrol.

. A

The heart of the frequency-determining system is an operational-transconductance-amplifier (OTA) (see Note 10), lC

, operated as a voltage-controlled current-source. The

output, I capacitor, C

, is a current applied directly to the integrating

, in the feedback loop of the integ r ator lC2, using

a CA3130, to provide the triangular-wav e output. Potentiometer R

is used to adjust the circuit for slope

symmetry of positive-going and negative-going signal excursions.

Another CA3130, IC

, is used as a controlled switch to set the

excursion limits of the triangular output from the integr a tor circuit. Capacitor C

is a “peaking adjustment” to optimize the

high-frequency square-wav e pe rformance of the circuit. Potentiometer R

is adjustable to perfect the “amplitude

symmetry” of the square-wave output signals. Output from the threshold detector is fed back via resistor R of lC

so as to toggle the current source from plus to minus

to the input

in generating the linear triangular wave.

Operation with Output-Stage Power-Booster

The current-sourcing and-sinking capability of the CA3130 output stage is easily supplemented to provide pow er-boost capability. In the circuit of Figure 17, three CMOS transistorpairs in a single CA3600E (see Note 12) lC arra y are sho wn parallel connected with the output stage in the CA3130. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the current-handling capability of the CA3130 output stage by about 2.5X.

The amplifier circuit in Figure 17 employs feedback to establish a closed-loop gain of 48dB. The typical large-signal bandwidth (-3dB) is 50kHz.

NOTE:

9. See file number 619 for technical information.

+15V

0.01µF

0.1µF 1µF

OFF-PERIOD

ADJUST

1MΩ

+ CA3130

0.001µF

PULSE PERIOD

4µs to 1ms 40µs to 10ms

0.4ms to 100ms 4ms to 1s

OUTPUT

2kΩ

ON-PERIOD

100kΩ

FREQUENCY RANGE:

FIGURE 15. PULSE GENERATOR (AST ABLE MUL TIVIBRA TOR)

ADJUST

1MΩ

2kΩ 2kΩ

100kΩ

1µF

0.1µF

0.01µF

POSITION OF S

0.001µF

WITH PROVISIONS FOR INDEPE NDENT CON TR OL OF “ON” AND “OFF” PERIODS

NOTE:

10. See file number 475 and AN6668 for technical information.

FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)

+15V

2kΩ

CA3130

NOTES:

11. Transistors Q

, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.

12. See file number 619.

FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130

Typical Performance Curves (Continued)

CA3130, CA3130A

17.5 LOAD RESISTANCE =

TA = 25oC

12.5

V- = 0

7.5

2.5

QUIESCENT SUPPLY CURRENT (mA)

6 8 10 12 14 16 18

∞

OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+ OR LOW = V-

TO TAL SUPPLY VOLTAGE (V)

FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

NEGATIVE SUPPLY VOLTAGE = 0V

= 25oC

0.1

POSITIVE SUPPLY VOLTAGE = 5V

10V

15V

OUTPUT VOLTAGE = V+/2

V- = 0

QUIESCENT SUPPLY CURRENT (mA)

0246810121416

TOTAL SUPPLY VOLTAGE (V)

TA = -55oC

125oC

FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

NEGATIVE SUPPLY VOLTAGE = 0V T

= 25oC

POSITIVE SUPPLY VOLTAGE = 5V

0.1

10V

15V

25oC

STAGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACRO SS PMOS OUTPUT

0.001

0.001 0.01 0.1 1.0 10 100 MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR

) vs LOAD CURRENT

ST AGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACROSS NMOS OUTPUT

0.001

0.001 0.01 0.1 1 10 100 MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR

(Q12) vs LOAD CURRENT

Dual-In-Line Plastic Packages (PDIP)

CA3130, CA3130A

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45°

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC H 0.2284 0.2440 5.80 6.20 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 87

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

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intersil CA3130, CA3130A DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual