intersil CA3130, CA3130A DATA SHEET

CA3130, CA3130A

Data Sheet August 1, 2005 FN817.6

15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

CA3130A and CA3130 are op amps that combine the advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS transistors in the input stage results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit.

The CA3130 Series circuits operate at supply voltages ranging from 5V to 16V, (±2.5V to ±8V). They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage.

• The CA3130A offers superior input characteristics over those of the CA3130.

Ordering Information

PART NO.

(BRAND)

CA3130AE CA3130AM

(3130A)

CA3130AM96

(3130A)

CA3130AMZ

(3130AZ) (Note)

CA3130AMZ96

(3130AZ) (Note)

CA3130E CA3130EZ

(Note) CA3130M

(3130)

CA3130M96

(3130)

CA3130MZ

(3130MZ) (Note)

CA3130MZ96

(3130MZ)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TEMP.

RANGE (

C) PACKAGE

-55 to 125 8 Ld PDIP E8.3

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

-55 to 125 8 Ld PDIP E8.3

-55 to 125 8 Ld PDIP* (Pb-free)

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

DWG. #

M8.15

E8.3

M8.15

PKG.

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5 TΩ (1.5 x 1012Ω) (Typ)

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

. . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators (Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• Voltage Followers (e.g. Follower for Single-Supply D/A Converter)

• Voltage Regulators (Permits Control of Output Voltage Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

Pinout

CA3130, CA3130A

(PDIP, SOIC)

TOP VIEW

OFFSET

NON-INV.

NULL

INV.

INPUT INPUT

1 2

3 4

V-

8 7 6 5

STROBE V+ OUTPUT OFFSET

NULL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

CA3130, CA3130A

Absolute Maximum Ratings

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+

+8V) to (V- -0.5V)

Input-Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -50

C to 125oC

Thermal Information

Thermal Resistance (Typical, Note 2) θ

PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder process-

(oC/W) θJC (oC/W)

C to 150oC

ing only. They are not intended for use in Reflow solder processing applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply. is measured with the component mounted on an evaluation PC board in free air.

2. θ

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage |V Input Offset Voltage

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

TEST

CA3130 CA3130A

CONDITIONS

|VS = ±7.5V - 8 15 - 2 5 mV

∆V

/∆T - 10 - - 10 - µV/oC

UNITSMIN TYP MAX MIN TYP MAX

Temperature Drift Input Offset Current |I Input Current I Large-Signal Voltage Gain A

Common-Mode

|VS = ±7.5V - 0.5 30 - 0.5 20 pA

VS = ±7.5V - 5 50 - 5 30 pA VO = 10V

RL = 2kΩ

P-P

50 320 - 50 320 - kV/V 94 110 - 94 110 - dB

CMRR 70 90 - 80 90 - dB

Rejection Ratio Common-Mode Input

Voltage Range Power-Supply

Rejection Ratio Maximum Output Voltage V

Maximum Output Current I

Supply Current I+ V

ICR

/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V

∆V

+RL = 2kΩ 12 13.3 - 12 13.3 - V

-RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

+RL = ∞ 14.99 15 - 14.99 15 - V

-RL = ∞ - 0 0.01 - 0 0.01 V

+ (Source) at VO = 0V 12 22 45 12 22 45 mA

- (Sink) at VO = 15V 12 20 45 12 20 45 mA

= 7.5V,

= ∞

I+ V

= 0V, = ∞

0 -0.5 to 12 10 0 -0.5 to 12 10 V

- 10 15 - 10 15 mA

-23-23mA

CA3130, CA3130A

Electrical Specifications Typical Values Intended Only for Design Guidance, V

Unless Otherwise Specified

= ±7.5V, TA = 25oC

SUPPLY

CA3130,

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or

CA3130A UNITS

±22 mV

4 and 1 Input Resistance R Input Capacitance C Equivalent Input Noise Voltage e

Open Loop Unity Gain Crossover Frequency (For Unity Gain Stability ≥47pF Required.)

I I

f = 1MHz 4.3 pF

BW = 0.2MHz, RS = 1MΩ

(Note 3)

CC = 0 15 MHz

= 47pF 4 MHz

1.5 TΩ

23 µV

Slew Rate: SR

= 0 30 V/µsOpen Loop

Closed Loop C

= 56pF 10 V/µs

Transient Response: CC = 56pF,

= 25pF,

Overshoot OS 10 %

Settling Time (To <0.1%, V

= 4V

P-P

= 2kΩ

(Voltage Follower)

0.09 µsRise Time t

1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of R

up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T

Unless Otherwise Specified (Note 4)

= 25oC

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage V Input Offset Current I Input Current I

82mV

0.1 0.1 pA 22pA

Common-Mode Rejection Ratio CMRR 80 90 dB Large-Signal Voltage Gain A

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

ICR

Supply Current I+ V

Power Supply Rejection Ratio ∆V

/∆V+ 200 200 µV/V

= 5V, RL = ∞ 300 300 µA

= 2.5V, RL = ∞ 500 500 µA

0 to 2.8 0 to 2.8 V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25

Schematic Diagram

1 8 4

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 1, provide the total gain of the CA3130. A biasing circuit provides two potentials for common use in the first and second stages.

Terminal 8 can be used both for phase compensation and to strobe the output stage into qui esce nce . When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply-rail potential at Terminal 7. This condition of essentially zero current drain in

the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g.,when the amplifier output is used to drive CMOS digital circuits in Comparator applications).

Input Stage

The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q transistors (Q with resistors R

The mirror-pair transistors also function as a differential -tosingle-ended converter to provide base driv e to the se con dstage bipolar transistor (Q can be effected by connecting a 100,00 0Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4.

, Q7) working into a mirror-pair of bipolar

, Q10) functioning as load resistors together

through R6.

). Offset nulling, when desired,

CA3130, CA3130A

CA3130

INPUT

200µA 200µA

AV ≈ 5X

1.35mA

BIAS CKT.

AV ≈

6000X

8mA (NOTE 5) 0mA (NOTE 7)

≈

30X

COMPENSATION

OFFSET

NULL

NOTES:

6. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4.

7. T otal supply v oltage (f or indicated voltage gains) = 15V with output terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

(WHEN REQUIRED)

815

STROBE

V+

OUTPUT

V-

Cascade-connected PMOS transistors Q2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described.

The small diodes D

through D8 provide gate-oxide protection

against high-voltage transients , incl uding static ele ctricity during handling for Q

and Q7.

Second-Stage

Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q

and its cascade-connected load resistance provided by PMOS transistors Q

and Q5. The source of bias potentials

for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, some w hat above 8.3V, resistor R2 and zener diode Z the series-connected circuit, consisting of resistor R D

through D4, and PMOS transistor Q1. A tap at the junction

of resistor R about 4.5V for PMOS transistors Q Terminal 7. A potential of about 2.2V is developed across diode-connected PMOS transistor Q 7 to provide gate bias for PMOS transistors Q should be noted that Q both Q

and Q3. Since transistors Q1, Q2, Q3 are designed to

be identical, the approximately 200µA current in Q establishes a similar curr ent in Q

serve to establish a voltage of 8.3V across

and diode D4 provides a gate-bias potential of

is “mirror-connected (see Note 8)” to

and Q5 with respect to

with respect to T erminal

and Q3 as constant current

, diodes

and Q3. It

sources for both the first and second amplifier stages, respectively.

At total supply voltages somewhat less than 8.3V, zener diode Z developed across series-connected R

becomes nonconductive and the potential,

, D1-D4, and Q1,

varies directly with variations in supply voltage. Consequently, the gate bias for Q

, Q5 and Q2, Q3 varies in

accordance with supply-voltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 2. Typical op amp loads are readily driven by the output stage. Because largesignal excursions are non-linear, requiring feedback f or good waveform reproduction, transient delays may be encountered. As a voltage follower , the amplifier can achiev e

0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transistor-pairs in linear-circuit applications, see File Number 619, data sheet on CA3600E “CMOS Transistor Array”.

17.5 SUPPLY VOLTAGE: V+ = 15, V- = 0V

= 25oC

12.5

500Ω

7.5

2.5

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 2. VOL TAGE TRANSFER CHARACTERISTICS OF

LOAD RESISTANCE = 5kΩ

2kΩ

1kΩ

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

CMOS OUTPUT STAGE

17.5 2012.5 15107.52.5 50

22.5

CA3130, CA3130A

Input Current Variation with Common Mode Input Voltage

As shown in the Table of Electrical Specifications, the input current for the CA3130 Series Op Amps is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common-mode potential of +7.5V with respect to negative supply T erminal 4. Figure 3 contains data showing the variation of input current as a function of common-mode input voltage at TA = 25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate-protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to Terminal 4 potential, and the Metal Can case of the CA3130 is also internally tied to T erminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents.

TA = 25oC

7.5

INPUT VOLTAGE (V)

2.5

-101234567

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

INPUT CURRENT (pA)

CA3130

V+

15V

-10V

V-

Offset Nulling

Offset-voltage nulling is usually accomplished with a 100,000Ω potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset-null adjustment usually can be effected with the slider arm positioned in the mid-point of the potentiometer’s total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate-protective diodes in the input circuit. As with any semiconductor-junction device, including op amps with a junction-FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 4 provides data on the

typical variation of input bias current as a function of temperature in the CA3130.

4000

VS = ±7.5V

1000

100

INPUT CURRENT (pA)

-80 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

In applications requiring the lowest practical input current and incremental increases in current because of “warm-up” effects, it is suggested that an appropriate heat sink be used with the CA3130. In addition, when “sinking” or “sourcing” significant output current the chip temperature increases, causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input current variations.

Input Offset Voltage (VIO) Variation with DC Bias and Device Operating Life

It is well known that the characteristics of a MOSFET device can change slightly when a DC gate-source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA3130 should be alert to the possible impacts of this effect if the application of the device involves e xtended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 5 shows typical data pertinent to shifts in offset voltage encountered with CA3130 devices (metal can package) during life testing. At lower temperatures (metal can and plastic), for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2VDC differential voltage example represents conditions when the amplifier output stage is “toggled”, e.g., as in comparator applications.

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