Intersil Corporation CA3102 Datasheet
CA3102
Data Sheet November 1999
Dual High FrequencyDifferentialAmplifier
For Low Power Applications Up to
500MHz
The CA3102 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of f
in excess of 1GHz.
T
These features make the CA3102 useful from DC to
500MHz. Bias and load resistors have been omitted to
provide maximum application flexibility.
The monolithic construction of the CA3102 provides close
electrical and thermal matching of the amplifiers. This
feature makes this device particularly useful in dual channel
applications where matched performance of the two
channels is required.
The CA3102has a separate substrate connection for greater
design flexibility.
Ordering Information
PART NUMBER
(BRAND)
CA3102E -55 to 125 14 Ld PDIP E14.3
CA3102M
(3102)
TEMP.
RANGE (oC) PACKAGE
-55 to 125 14 Ld SOIC M14.15
PKG.
NO.
File Number 611.6
Features
• Power Gain 23dB (Typ). . . . . . . . . . . . . . . . . . . . . 200MHz
• Noise Figure 4.6dB (Typ) . . . . . . . . . . . . . . . . . . . 200MHz
• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
o
• Full Military Temperature Range . . . . . . . -55
C to 125oC
Applications
• VHF Amplifiers
• VHF Mixers
• Multifunction Combinations - RF/Mixer/Oscillator;
Converter/IF
• IF Amplifiers (Differential and/or Cascode)
• Product Detectors
• Doubly Balanced Modulators and Demodulators
• Balanced Quadrature Detectors
• Cascade Limiters
• Synchronous Detectors
• Balanced Mixers
• Synthesizers
• Balanced (Push-Pull) Cascode Amplifiers
• Sense Amplifiers
Pinout
CA3102
(PDIP, SOIC)
TOP VIEW
1
2
3
4
SUBSTRATE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207
5
6
7
| Copyright © Intersil Corporation 1999
14
13
12
SUBSTRATE
11
10
9
8
CA3102
Absolute Maximum Ratings Thermal Information
Collector-to-Emitter Voltage, V
Collector-to-Base Voltage, V
Collector-to-Substrate Voltage, V
Emitter-to-Base Voltage, V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode.The substrate (Terminal 9) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
. . . . . . . . . . . . . . . . . . . . . . 15V
CEO
. . . . . . . . . . . . . . . . . . . . . . . . 20V
CBO
(Note 1). . . . . . . . . . . . . . 20V
CIO
. . . . . . . . . . . . . . . . . . . . . . . . . . 5V
EBO
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications T
= 25oC
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage (Figures 1, 4) V
Input Offset Current (Figure 1) I
Input Bias Current (Figures 1, 5) I
Temperature Coefficient
Magnitude of Input Offset Voltage
∆V
----------------
∆T
IO
IO
B
I3 = I9 = 2mA - 0.3 3.0 µA
IO
- 0.25 5.0 mV
- 13.5 33 µA
- 1.1 - µV/oC
DC CHARACTERISTICS FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
VBE VCE = 6V, IC = 1mA 674 774 874 mV
(Figure 6)
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
Collector Cutoff Current (Figure 7) I
Collector-to-Emitter Breakdown Voltage V
Collector-to-Base Breakdown Voltage V
Collector-to-Substrate Breakdown Voltage V
Emitter-to-Base Breakdown Voltage V
∆V
-------------- -
∆T
CBO
(BR)CEOIC
(BR)CBOIC
(BR)CIOIC
(BR)EBOIE
VCE = 6V, IC = 1mA - -0.9 - mV/oC
BE
VCB = 10V, IE = 0 - 0.0013 100 nA
= 1mA, IB = 0 15 24 - V
= 10µA, IE = 0 20 60 - V
= 10µA, IB = IE = 0 20 60 - V
= 10µA, IC = 0 5 7 - V
DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
1/f Noise Figure (For Single Transistor)
(Figure 12)
Gain Bandwidth Product (For Single
NF f = 100kHz, RS = 500Ω,
IC = 1mA
f
T
VCE = 6V, IC = 5mA - 1.35 - GHz
- 1.5 - dB
Transistor) (Figure 11)
Collector-Base Capacitance (Figure 8) C
Collector-Substrate
CB
C
CI
IC = 0,
VCB = 5V
Note 3 - 0.28 - pF
Note 4 - 0.15 - pF
IC = 0, VCI = 5V - 1.65 - pF
Capacitance (Figure 8)
Common Mode Rejection Ratio CMRR I3 = I9 = 2mA - 100 - dB
AGC Range, One Stage (Figure 2) AGC Bias Voltage = -6V - 75 - dB
Voltage Gain, Single-Ended Output
(Figures 2, 9, 10)
A Bias Voltage = -4.2V,
f = 10MHz
18 22 - dB
2
CA3102
Electrical Specifications T
= 25oC (Continued)
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Insertion Power Gain (Figure 3) G
Noise Figure (Figure 3) NF Cascode - 4.6 - dB
Input Admittance Y
Reverse Transfer Admittance Y
11
12
VCC = 12V, for
P
Cascode
Configuration
I3=I9= 2mA. For
Diff. Amp.
Configuration
I3=I9= 4mA (Each
Collector IC≅ 2mA)
f = 200MHz
Cascode - 23 - dB
Cascode (Figures
- 1.5 + j2.45 - mS
14, 16, 18)
Diff. Amp. (Figures
- 0.878 + j1.3 - mS
15, 17, 19)
Cascode - 0.0 - j0.008 - mS
Diff. Amp. - 0.0 - j0.013 - mS
Forward Transfer
Admittance
Y
21
Cascode (Figures
- 17.9 - j30.7 - mS
26, 28, 30)
Diff. Amp. (Figures
- -10.5 + j13 - mS
27, 29, 31)
Output Admittance Y
22
Cascode (Figures
- -0.503 - j15 - mS
20, 22, 24)
Diff. Amp. (Figures
- 0.071 + j0.62 - mS
21, 23, 25)
NOTES:
3. Terminals 1 and 14 or 7 and 8.
4. Terminals 13 and 4 or 6 and 11.
Schematic Diagram
11413 4
Q
2
Q
2
1
Q
3
3
CA3102E, CA3102M
12
10
5
SUBSTRATE
8 11
7 6
Q
Q
6
5
Q
4
9
3
Test Circuits
+1V
1kΩ
-1V
V+ (+6V)
1kΩ 1kΩ
S
2
S
1
V
CA3102
+6V
1kΩ
13 (6)14(7)
S
O
2
MM
S
1
V
IN
10µF
(8)
1
100Ω
BIAS
VOLTAGE
Q
2
(Q6)
(10)
2
5
(Q5)
Q3 (Q4)
3
(9)
Q
1
100Ω
V
OUT
(11)
4
V
M
I
V- (-6V)
3
or I
9
X
12
500Ω
-6V
FIGURE 1. DC CHARACTERISTICS TEST CIRCUIT FOR CA3102 FIGURE 2. AGCRANGE AND VOLTAGEGAIN TEST CIRCUIT
FOR CA3102
1/2 CA3102
14(7)
R
INPUT
= 50Ω
G
0.005µF
5(12)
5.6pF
Q
2
1(8)
SUBSTRATE
5µF
C
L
1
1
(Q6)
100Ω
Q
1
(Q5)
(Q4)
Q
3
3 (9)2 (10) 4 (11) 13 (6)
6V
2+
0.001
µF
5pF
0.001µF
2.7pF
C
2
L
2
OUTPUT
RL = 50Ω
0.001µF
+12V
2kΩ
100pF
0.001µF
1kΩ
100pF
MA
5kΩ
FERRITE
BEADS
13kΩ
0.001µF
100pF
NOTES:
5. Numbers in parentheses refer to the other
half of the CA3102.
6. L1,L2- Approximately1/2Turn #18 Tinned
Copper Wire, 5/8” Diameter.
470pF
10kΩ
0.001µF
7. C1,C2- 15pF VariableCapacitors
(Hammarlund, MAC-15; or Equivalent).
FIGURE 3. 200MHz CASCODE POWER GAIN AND NOISE FIGURE TEST CIRCUIT
4
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