Intersil Corporation CA3524, CA2524, CA1524 Datasheet

7-16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 407-727-9207
| Copyright © Intersil Corporation 1999
CA1524, CA2524
CA3524
Regulating Pulse Width Modulator
Description
The CA1524, CA2524, and CA3524 have all the features of the industry types SG1524, SG2524, and SG3524, respectively. A block diagram of the CA1524 series is shown in Figure 1. The circuit includes a zener voltage reference, transconductance error amplifier, precision R-C oscillator, pulse-width modulator, pulse-steering flip-flop, dual alternat­ing output switches, and current-limiting and shutdown circuitry. This device can be used for switching regulators of either polarity, transformer-coupled dc-dc converter, transformerless voltage doublers, dc-ac power inverters, highly efficient variable power supplies, and polarity converter, as well as other power-control applications.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE PACKAGE
CA1524E -55oC to +125oC 16 Lead Plastic DIP CA1524F -55oC to +125oC 16 Lead CerDIP CA2524E 0oC to +70oC 16 Lead Plastic DIP CA2524F 0oC to +70oC 16 Lead CerDIP CA3524E 0oC to +70oC 16 Lead Plastic DIP CA3524F 0oC to +70oC 16 Lead CerDIP
Features
• Complete PWM Power Control Circuitry
• Line and Load Regulation. . . . . . . . . . . . . . . 0.2% (Typ)
• Internal Reference Supply with 1% (Max) Oscillator and Reference Voltage Variation Over Full Temperature Range
• Standby Current of Less Than 10mA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.5µs to 5µs
• Low V
CE(sat)
Over the Temperature Range
Applications
• Positive and Negative Regulated Supplies
• Dual-Output Regulators
• Flyback Converters
• DC-DC Transformer-Coupled Regulating Converters
• Single-Ended DC-DC Converters
• Variable Power Supplies
File Number
1239.3
Pinout
CA1524, CA2524, CA3524
(PDIP, CERDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
C
T
R
T
V
REF
EMITTER B COLLECTOR B
COLLECTOR A EMITTER A
SHUTDOWN
INV. INPUT
OSC OUT
GND
(-) C.L.
SENSE
(+) C.L. SENSE
V+
COMPENSATION AND COMPARATOR
NON-
INV. INPUT
April 1994
7-17
CA1524, CA2524, CA3524
Functional Block Diagram
Test Circuit
REFERENCE REGULATOR
5V
FLIP
OSCILLATOR
COMPARATOR
INV. INPUT
NON-INV. INPUT
ERROR
AMP
SHUTDOWN
GND
16
15
3
6
7
1
2
10
8
FLOP
+5V
+5V TO ALL INTERNAL CIRCUITS
+5V
-
+
+5V
+5V
C.L.
+5V
+
-
10k
1k
9
5
4
COMPENSATION AND COMPARATOR
- SENSE
+ SENSE
12
11
S
A
E
A
C
A
13
14
S
B
E
B
C
B
C
T
R
T
OSC OUT
V
REF
V+
12
13
11
14
5410912768
16
15
3
ls
CA1524
V+
8 - 40V
0.1µF
R
T
C
T
2k
10k
1k
10
k
2k
2k
2k
1W
2k 1W
OUT A
OUT B
7-18
Specifications CA1524, CA2524, CA3524
Absolute Maximum Ratings Thermal Information
Input Voltage (Between VIN and GND Terminals) . . . . . . . . . . . 40V
Operating Voltage Range (VIN to GND) . . . . . . . . . . . . . . . .8 to 40V
Output Current Each Output:
(Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Output Current (Reference Regulator). . . . . . . . . . . . . . . . . . .50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mA
Thermal Resistance θ
JA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W
Device Dissipation
Up to TA = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Above TA = +25oC. . . . . . . . . . . . . . .Derate Linearly at 10mW/oC
Operating Temperature Range . . . . . . . . . . . . . . . .-55oC to +125oC
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
A
= -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated.
PARAMETER TEST CONDITIONS
CA1524, CA2524 CA3524
UNITSMIN TYP MAX MIN TYP MAX
REFERENCE SECTION Output Voltage 4.8 5 5.2 4.6 5 5.4 V Line Regulation V+ = 8 to 40V - 10 20 - 10 30 mV Load Regulation IL = 0 to 20mA - 20 50 - 20 50 mV Ripple Rejection f = 120Hz, TA = 25oC - 66 - - 66 - db Short Circuit Current Limit V
REF
= 0, TA = 25oC - 100 - - 100 - mA
Temperature Stability Over Operating Temperature
Range
- 0.3 1 - 0.3 1 %
Long Term Stability TA = 25oC - 20 - - 20 - mV/khr OSCILLATOR SECTION Maximum Frequency CT = 0.001µF, RT = 2K - 300 - - 300 - kHz Initial Accuracy RT and CT Constant - 5 - - 5 - % Voltage Stability V+ = 8 to 40V, TA = 25oC--1--1% Temperature Stability Over Operating Temperature
Range
--2--2 %
Output Amplitude Terminal 3, TA = 25oC - 3.5 - - 3.5 - V Output Pulse Width (Pin 3) CT = 0.01µF, TA = 25oC - 0.5 - - 0.5 - µs Ramp Voltage Low (Note 1) Pin 7 - 0.6 - - 0.6 - V Ramp Voltage High (Note 1) Pin 7 - 3.5 - - 3.5 - V Capacitor Charging Current Range Pin 7 (5-2 VBE)/R
T
0.03 - 2 0.03 - 2 mA Timing Resistance Range Pin 6 1.8 - 120 1.8 - 120 k Charging Capacitor Range Pin 7 0.001 - 0.1 0.001 - 0.1 µF Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)
Pin 3 100 - 1000 100 - 1000 pF
ERROR AMPLIFIER SECTION Input Offset Voltage VCM = 2.5V - 0.5 5 - 2 10 mV Input Bias Current VCM = 2.5V - 1 10 - 1 10 µA Open Loop Voltage Gain 72 80 - 60 80 - dB Common Mode Voltage TA = 25oC 1.8 - 3.4 1.8 - 3.4 V Common Mode Rejection Ratio TA = 25oC - 70 - - 70 - dB Small Signal Bandwidth AV = 0dB, TA = 25oC - 3 - - 3 - MHz
7-19
Specifications CA1524, CA2524, CA3524
Output Voltage TA = 25oC 0.5 - 3.8 0.5 - 3.8 V Amplifier Pole - 250 - - 250 - Hz Pin 9 Shutdown Current External Sink - 200 - - 200 - µA COMPARATOR SECTION Duty Cycle % Each Output On 0 - 45 0 - 45 % Input Threshold Zero Duty Cycle - 1 - - 1 - V Input Threshold Max. Duty Cycle - 3.5 - - 3.5 - V Input Bias Current - 1 - - 1 - µA CURRENT LIMITING SECTION Sense Voltage for 25% Output Duty
Cycle
Terminal 9 = 2V with Error Amplifier Set for Max Out, TA = 25oC
190 200 210 180 200 220 mV
Sense Voltage T.C. - 0.2 - - 0.2 - mV/oC Common Mode Voltage -1 - +1 -1 - +1 V Rolloff Pole of R51 C3 + Q64 - 300 - - 300 - Hz OUTPUT SECTION (EACH OUTUT) Collector-Emitter Voltage 40 - - 40 - - V Collector Leakage Current VCE = 40V - 0.1 50 - 0.1 50 µA Saturation Voltage V+ = 40V, IC = 50mA - 0.8 2 - 0.8 2 V Emitter Output Voltage V+ = 20V 17 18 - 17 18 - V Rise Time RC = 2K, TA = 25oC - 0.2 - - 0.2 - µs Fall Time RC = 2K, TA = 25oC - 0.1 - - 0.1 - µs Total Standby Current: (Note 2) I
S
V+ = 40V - 4 10 - 4 10 mA
NOTES:
1. Ramp voltage at Pin 7 where t = OSC period in microseconds
t RTCT with CT in microfarads and RT in ohms. Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency when each output is connected in parallel.
2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.
Electrical Specifications T
A
= -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated. (Continued)
PARAMETER TEST CONDITIONS
CA1524, CA2524 CA3524
UNITSMIN TYP MAX MIN TYP MAX
High Low
t
7-20
CA1524, CA2524, CA3524
Schematic Diagram
21
3
7
6
8
Q1
R1
500
R5 1K
R7 1K
Q2
Q7
Q13
Q6
Q3 Q4
R2
2.7K
RC
10K
R3
6.3K
Q10
Q11
D2
D1
Q9
C1
20pF
R4
500
R6
500
Q5 Q12
RB
4.8K
RA
5.3K
QA
OSC SECTION
Q42 Q43
Q44
Q47 Q48
Q49 Q50
Q45
Q46
R39 1K
R41 24K
R40
560
R42
19.8K
Q51
Q52
R45 25K
R44
1.8K
R43
7.4K
Q53
Q54
Q55
R46
3.3K
OSC.
OUT
Q59 Q60
Q61
Q56 Q57
INV.
IN
ERROR
AMP
NON-INV. INPUT
Q58 Q62
R471KR48
2K
J
K L
F G H
I
C
D E
Q24
Q22
Q20
R15 25K
C2
20pF
N
+
P
10K 1.9K
RD
Q19
R14 450
Q14 Q15
R8
8.4K
R9 500
R10 1K
Q17
Q18
R11 500
R12 10K
Q16
R13
6
15
V
IN
C4
PULSE STEERING FLIP-FLOP
B
A
R16
16.2K
R19
18.7 K
R17
18.7 K
R18
18.7 K
R18
18.7 K
Q21 Q23
16
V
REF
+5V
GND
R
T
C
T
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