Intersil Corporation AD7541 Datasheet

AD7541

August 1997

Features

• 12-Bit Linearity 0.01%

• Pretrimmed Gain

• Low Gain and Linearity Tempcos

• Full Temperature Range Operation

• Full Input Static Protection

• TTL/CMOS Compatible

• +5V to +15V Supply Range

Description

The AD7541 is a monolithic, low cost, high performance, 12-bit accurate, multiplying digital-to-analog converter (DAC).

Intersil’ wafer level laser-trimmed thin-ﬁlm resistors on CMOS circuitry provide true 12-bit linearity with TTL/CMOS compatible operation.

Special tabbed-resistor geometries (improving time stability), full input protection from damage due to static discharge by diode clamps to V+ and ground, large I

12-Bit, Multiplying D/A Converter

lines (improving superposition errors) are some of the fea-

• 20mW Low Power Dissipation

• Current Settling Time 1µs to 0.01% of FSR

• Four Quadrant Multiplication

tures offered by Intersil AD7541. Pin compatible with AD7521, this DAC provides accurate

four quadrant multiplication over the full military temperature range.

Ordering Information

PART NUMBER NONLINEARITY TEMP. RANGE (oC) PACKAGE PKG. NO.

AD7541JN 0.02% (11-Bit) 0 to 70 18 Ld PDIP E18.3

OUT1

and I

OUT2

bus

AD7541KN 0.01% (12-Bit) 0 to 70 18 Ld PDIP E18.3

AD7541LN 0.01% (12-Bit) Guaranteed

Monotonic

Pinout

AD7541

(PDIP)

TOP VIEW

OUT1

OUT2

GND

BIT 1 (MSB)

BIT 2 BIT 3 BIT 4 BIT 5 BIT 6

1 2 3 4 5 6 7 8 9

FEEDBACK

REF IN

V+

BIT 12 (LSB)

BIT 11 BIT 10

BIT 9

BIT 8

BIT 7

Functional Block Diagram

REF IN

(17)

SWITCHES

NOTE: Switches shown for digital inputs “High”.

0 to 70 18 Ld PDIP E18.3

10kΩ 10kΩ 10kΩ 10kΩ

SPDT NMOS

MSB

(4)

BIT 3BIT 2

(5) (6)

20kΩ20kΩ20kΩ20kΩ20kΩ

10kΩ

20kΩ

(3)

(2)

OUT2

(1)

OUT1

FEEDBACK

(18)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

10-9

File Number 3107.1

AD7541

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

REF

Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND

Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+

Operating Conditions

Temperature Range

JN, KN, LN Versions. . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

Electrical Speciﬁcations V+ = +15V, V

PARAMETER TEST CONDITIONS

= +10V, V

REF

OUT1

= V

= 0V, TA = 25oC, Unless Otherwise Speciﬁed

OUT2

TA = 25oCT

MIN-MAX

UNITSMIN TYP MAX MIN MAX

SYSTEM PERFORMANCE

Resolution 12 - - 12 - Bits Nonlinearity A, S, J -10V ≤ V

B, T, K - - ±0.012 - ±0.012 % of FSR L--±0.012 - ±0.012 % of FSR

OUT1

See Figure 3 (Note 5)

= V

REF

≤ +10V

OUT2

--±0.024 - ±0.024 % of FSR

= 0V

Monotonicity Guaranteed Gain Error -10V ≤ V Output Leakage Current

OUT1

≤ +10V (Note 5) - - ±0.3 - ±0.4 % of FSR

REF

= V

= 0 - - ±50 - ±200 nA

OUT2

(Either Output)

DYNAMIC CHARACTERISTICS

Power Supply Rejection V+ = 14.5V to 15.5V

See Figure 5 (Note 5)

Output Current Settling Time To 0.1% of FSR

--±0.005 - ±0.01 % of FSR/% of ∆V+

--1-1 µs

See Figure 9 (Note 6)

Feedthrough Error V

REF

= 20V

P-P

, 10kHz

--1-1mV

All Digital Inputs Low See Figure 8 (Note 6)

REFERENCE INPUTS

Input Resistance All Digital Inputs High

at Ground

OUT1

5 10 20 5 20 kΩ

ANALOG OUTPUT

Voltage Compliance Both Outputs, See Maximum

-100mV to V+

Ratings (Note 7)

Output Capacitance C

C C C

OUT1 OUT2 OUT1 OUT2

All Digital Inputs High See Figure 7 (Note 6)

All Digital Inputs Low) See Figure 7 (Note 6)

- - 200 - 200 pF

- - 60 - 60 pF

- - 200 - 200 pF

Output Noise (Both Outputs) See Figure 6 Equivalent to 10kΩ Johnson Noise

DIGITAL INPUTS

Low State Threshold, V High State Threshold, V

(Notes 2, 6) - - 0.8 - 0.8 V

2.4 - - 2.4 - V

P-P

10-10

AD7541

Electrical Speciﬁcations V+ = +15V, V

PARAMETER TEST CONDITIONS

Input Current VIN = 0V or V+ (Note 6) - - ±1-±1 µA Input Coding See Tables 1 and 2 (Note 6) Binary/Offset Binary Input Capacitance (Note 6) - - 8 - 8 pF

POWER SUPPLY CHARACTERISTICS

Power Supply Voltage Range Accuracy Is Not Guaranteed

Over This Range

I+ All Digital Inputs High or Low

(Excluding Ladder Network)

Total Power Dissipation (Including Ladder Network) - 20 - - - mW

NOTES:

2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic ﬁelds. Keep unused units in conductive foam at all times.

3. Do not apply voltages higher than VDD or less than GND potential on any terminal except V

4. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.

5. Using internal feedback resistor, R

6. Guaranteed by design or characterization and not production tested.

7. Accuracy not guaranteed unless outputs at ground potential.

FEEDBACK

= +10V, V

REF

OUT1

= V

= 0V, TA = 25oC, Unless Otherwise Speciﬁed (Continued)

OUT2

TA = 25oCT

+5 to +16 V

- - 2.0 - 2.5 mA

REF

and R

MIN-MAX

FEEDBACK

UNITSMIN TYP MAX MIN MAX

Deﬁnition of Terms

Nonlinearity: Error contributed by deviation of the DAC

transfer function from a “best ﬁt straight line” function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire V range.

Resolution: Value of the LSB. For example, a unipolar converter with n bits has a resolution of LSB = (V bipolar converter of n bits has a resolution of LSB=(V

Settling Time: Time required for the output function of the DAC to settle to within

REF

)/2

-(N-1)

. Resolution in no way implies linearity.

/2 LSB for a given digital input

stimulus, i.e., 0 to Full Scale. Gain Error: Ratio of the DAC’s operational ampliﬁer output

voltage to the nominal input voltage value. Feedthrough Error: Error caused by capacitive coupling

from V Output Capacitance: Capacitance from I

to output with all switches OFF.

REF

OUT1

, and I

terminals to ground. Output Leakage Current: Current which appears on

, terminal when all digital inputs are LOW or on I

OUT1

terminal when all inputs are HIGH.

REF

)/2-N. A

OUT2

Detailed Description

The AD7541 is a 12-bit, monolithic, multiplying D/A converter. A highly stable thin ﬁlm R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit. CMOS level shifters provide low power TTL/CMOS compatible operation. An external voltage or current reference and an operational ampliﬁer are all that is required for most voltage output applications. A simpliﬁed equivalent circuit of the DAC is shown on page 1, (Functional Diagram). The NMOS SPDT switches steer the ladder leg currents between I I

buses which must be held at ground potential. This

OUT2

conﬁguration maintains a constant current in each ladder leg independent of the input code. Converter errors are further eliminated by using wider metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset (leakage) errors to a negligible level.

Each circuit is laser-trimmed, at the wafer level, to better than 12-bits linearity. For the ﬁrst four bits of the ladder, special trim-tabbed geometries are used to keep the body of the resistors, carrying the majority of the output current, undisturbed. The resultant time stability of the trimmed circuits is comparable to that of untrimmed units.

The level shifter circuits are comprised of three inv erters with a positive feedback from the output of the second to ﬁrst (Figure 1). This conﬁguration results in TTL/COMS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binary weighted for an “ON” resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistor, resulting in accurate leg currents.

OUT1

and

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