intersil AD7520, AD7521 DATA SHEET

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AD7520, AD7521

Data Sheet August 2002

10-Bit, 12-Bit, Multiplying D/A Converters

The AD7520 and AD7521 are monolithic, high accuracy, low
cost 10-bit and 12-bit resolution, multiplying digital-to-analog
converters (DAC). Intersil’s thin-film on CMOS processing
gives up to 10-bit accuracy with TTL/CMOS compatible
operation. Digital inputs are fully protected against static
discharge by diodes to ground and positive supply.

Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and attenuators, etc.

Ordering Information

TEMP.

PART

NUMBER

LINEARITY

(INL, DNL)

AD7520JN 0.2% (8-Bit) 0 to 70 16 Ld PDIP E16.3

AD7521LN 0.05% (10-

Bit)

RANGE

o

(

C) PACKAGE

PKG.

0 to 70 18 Ld PDIP E18.3

NO.

FN3104.4

Features

• AD7520, 10-Bit Resolution; 8-Bit Linearity

• AD7521, 12-Bit Resolution; 10-Bit Linearity

• Low Power Dissipation (Max). . . . . . . . . . . . . . . . . 20mW

o

• Low Nonlinearity Tempco at 2ppm of FSR/

• Current Settling Time to 0.05% of FSR . . . . . . . . . . 1.0µs

• Supply Voltage Range . . . . . . . . . . . . . . . . . ±5V to +15V

• TTL/CMOS Compatible

• Full Input Static Protection

C

Pinouts

I

OUT1

I

OUT2

GND

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

AD7520 (PDIP)

TOP VIEW

1

2

3

4

5

6

7

8

R

16

FEEDBACK

V

15

REF

14

V+

BIT 10 (LSB)

13

BIT 9

12

BIT 8

11

BIT 7

10

BIT 6

9

I

OUT1

I

OUT2

GND

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

AD7521 (PDIP)

TOP VIEW

1

2

3

4

5

6

7

8

9

18

R

FEEDBACK

V

17

REF

16

V+

15

BIT 12 (LSB)

14

BIT 11

13

BIT 10

12

BIT 9

11

BIT 8

BIT 7

10

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

AD7520, AD7521

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

REF

Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND

Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+

Operating Conditions

Temperature Ranges

JN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in
conductive foam at all times.

Do not apply voltages higher than V

or less than GND potential on any terminal except V

DD

o

C to 70oC

Thermal Resistance (Typical, Note 1) θ

16 Ld PDIP Package 90 N/A
18 Ld PDIP Package 80 N/A

Maximum Junction Temperature (Plastic Packages) . . . . . . . 150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

REF

and R

FEEDBACK

.

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

(oC/W) θJC (oC/W)

JA

o

C to 150oC

o

o

C

C

Electrical Specifications V+ = +15V, V

= +10V, TA = 25oC Unless Otherwise Specified

REF

AD7520 AD7521

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

SYSTEM PERFORMANCE (Note 2)

Resolution 10 10 10 12 12 12 Bits
Nonlinearity J (Note 3) (Figure 2)

-10V ≤ V

L -10V ≤ V

REF

REF

≤ +10V
≤ +10V

(Figure 2)

Nonlinearity Tempco -10V ≤ V

(Notes 3, 4)

REF

≤ +10V

--±0.2

(8-Bit)

--±0.05

(10-Bit)

-- ±2- - ±2 ppm of

-- -% of
FSR

--±0.05

(10-Bit)

% of
FSR

FSR/

Gain Error - ±0.3 - - ±0.3 - % of

FSR

Gain Error Tempco - - ±10 - - ±10 ppm of

FSR/

Output Leakage Current
(Either Output)

Over the Specified
Temperature Range

--±200 - - ±200 nA

DYNAMIC CHARACTERISTICS

Output Current Settling Time To 0.05% of FSR (All Digital

-1.0 - -1.0 - µs

Inputs Low To High And High
To Low) (Note 4) (Figure 7)

Feedthrough Error V

= 20V

REF

All Digital Inputs Low (Note 4)

P-P

, 100kHz

- - 10 - - 10 mV

P-P

(Figure 6)

REFERENCE INPUT

Input Resistance All Digital Inputs High

I

at Ground

OUT1

5 10 20 5 10 20 kΩ

ANALOG OUTPUT

Output Capacitance I

All Digital Inputs High

OUT1

(Note 4) (Figure 5)

I

OUT2

All Digital Inputs Low

I

OUT1

(Note 4) (Figure 5)

I

OUT2

Output Noise Both Outputs

(Note 4) (Figure 4)

- 200 - - 200 - pF

-75--75-pF

-75--75-pF

- 200 - - 200 - pF

- Equivalent

to 10kΩ

- - Equivalent

to 10kΩ

- Johnson
Noise

DIGITAL INPUTS

Low State Threshold, V
High State Threshold, V
Input Current, I

, I

IL

IH

IL

IH

Over the Specified
Temperature Range
V

= 0V or +15V

IN

-- 0.8-- 0.8V

2.4 - - 2.4 - - V

-- ±1- - ±1 µA

Input Coding See Tables 1 and 2 Binary/Offset Binary

o

C

o

C

2

AD7520, AD7521

Electrical Specifications V+ = +15V, V

= +10V, TA = 25oC Unless Otherwise Specified (Continued)

REF

AD7520 AD7521

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX MIN TYP MAX

POWER SUPPLY CHARACTERISTICS

Power Supply Rejection V+ = 14.5V to 15.5V

(Note 3) (Figure 3)

- ±0.005 - - ±0.005 - %

FSR/%

∆V+

Power Supply Voltage Range +5 to +15 +5 to +15 V
I+ All Digital Inputs at 0V or V+

- ±1--±1-µA

Excluding Ladder Network
All Digital Inputs High or Low

-- 2-- 2mA

Excluding Ladder Network

Total Power Dissipation Including the Ladder Network - 20 - - 20 - mW

NOTES:

2. Full Scale Range (FSR) is 10V for Unipolar and ±10V for Bipolar modes.

3. Using internal feedback resistor R

FEEDBACK

.

4. Guaranteed by design, or characterization and not production tested.

5. Accuracy not guaranteed unless outputs at GND potential.

6. Accuracy is tested and guaranteed at V+ = 15V only.

Functional Diagram

V

REF

10kΩ 10kΩ 10kΩ 10kΩ

20kΩ20kΩ20kΩ20kΩ20kΩ

20kΩ

GND

SPDT NMOS

SWITCHES

NOTES:

BIT 3BIT 2MSB

Switches shown for Digital Inputs “High”.
Resistor values are typical.

Pin Descriptions

AD7520 AD7521 PIN NAME DESCRIPTION

11I
22I

OUT1

OUT2

3 3 GND Digital Ground. Ground potential for digital side of D/A.
4 4 Bits 1(MSB) Most Significant Digital Data Bit.
5 5 Bit 2 Digital Bit 2.
6 6 Bit 3 Digital Bit 3.
7 7 Bit 4 Digital Bit 4.
8 8 Bit 5 Digital Bit 5.

9 9 Bit 6 Digital Bit 6.
10 10 Bit 7 Digital Bit 7.
11 11 Bit 8 Digital Bit 8.
12 12 Bit 9 Digital Bit 9.
13 13 Bit 10 Digital Bit 10 (AD7521). Least Significant Digital Data Bit (AD7520).

- 14 Bit 11 Digital Bit 11 (AD7521).

- 15 Bit 12 Least Significant Digital Data Bit (AD7521).
14 16 V+ Power Supply +5V to +15V.
15 17 V
16 18 R

REF

FEEDBACK

Current Out summing junction of the R2R ladder network.
Current Out virtual ground, return path for the R2R ladder network.

Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
Feedback resistor used for the current to voltage conversion when using an external Op Amp.

10kΩ

I

OUT2

I

OUT1

R

FEEDBACK

3