Intersil Corporation ACTS573MS Datasheet

January 1996
ACTS573MS
Radiation Hardened Octal
Three-State Transparent Latch
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96725 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability. . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
12
RAD (Si)/s, 20ns Pulse
2
/mg
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current 1µA at VOL, VOH
• Fast Propagation Delay. . . . . . . . . . . . . . . . 18ns (Max), 12ns (Typ)
Description
The Intersil ACTS573MS is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable ( the data is latched. The output enable controls the three-state outputs. When the output enable pins ( impedance state. The latch operation is independent of the state of output enable.
The ACTS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family.
LE) is High. When the latch goes low
OE) are high the output is in a high
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
OE
D0 D1 D2 D3 D4 D5 D6 D7
GND
CDIP2-T20, LEAD FINISH C
TOP VIEW
1
OE
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7 8
D6
9
D7
GND
10
20 LEAD CERAMIC FLATPACK
CDFP4-F20, LEAD FINISH C
TOP VIEW
120 2 3 4 5 6 7 8 9 10
VCC
20
Q0
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13 12
Q7
11
LE
19 18 17 16 15 14 13 12 11
VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE
The ACTS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line package (D suffix).
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
5962F9672501VRC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP
5962F9672501VXC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack
ACTS573D/Sample 25oC Sample 20 Lead SBDIP
ACTS573K/Sample 25oC Sample 20 Lead Ceramic Flatpack
ACTS573HMSR 25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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Spec Number 518892
File Number 4092
Functional Diagram
Dn
ACTS573MS
1 OF 8 IDENTICAL CIRCUITS
LE
p n
LE
LE
p n
LE
OE
VCC
p
Qn
OE
n
VSS
COMMON CONTROLS
LE
LE
OE
LE
OE OE
TRUTH TABLE
OE LE DATA OUTPUT
LHHH
LHLL
LLlL
LLhH
HXXZ
NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch
Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518892
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