Intersil Corporation ACTS112MS Datasheet
January 1996
ACTS112MS
Radiation Hardened
Dual J-K Flip-Flop
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96714 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
-10
• Single Event Upset (SEU) Immunity: <1 x 10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
11
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability. . . . . . . . . . . >10
RAD (Si)/s, 20ns Pulse
12
RAD (Si)/s, 20ns Pulse
2
/mg
• Latch-Up Free Under Any Conditions
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
C to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay. . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ)
Description
The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop
with Set and Reset. The output change states on the negative transition
of the clock (CP1N or CP2N).
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
1
CP1
2
K1
3
J1
4
S1
5
Q1
6
Q1
7
Q2
8
GND
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
CP1
K1
J1
S1
Q1
Q1
Q2
GND
116
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
VCC
R1
R2
CP2
K2
J2
S2
Q2
The ACTS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
5962F9671401VEC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead SBDIP
5962F9671401VXC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack
ACTS112D/Sample 25oC Sample 16 Lead SBDIP
ACTS112K/Sample 25oC Sample 16 Lead Ceramic Flatpack
ACTS112HMSR 25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
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Spec Number 518825
File Number 3570.1
Functional Diagram
3(11)
J
2(12)
K
4(10)
S
15(14)
R
ACTS112MS
CL
P
N
CL
CL
P
N
CL
CL
CL
5 (9)
CL
P
N
P
CL
N
Q
6 (7)
Q
1(13)
CP
CL
CL
TRUTH TABLE
INPUTS OUTPUTS
S R CP J K Q Q
LHXXXHL
HLXXXLH
L L X X X H (Note 2) H (Note 2)
H H L L No Change
HH HLHL
HH LHLH
H H H H Toggle
H H H X X No Change
NOTE:
1. H = High Steady State, L = Low Steady State, X = Immaterial, = High-to-Low T ransition
2. Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the
Same Time
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518825
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