Intersil Corporation ACS573MS Datasheet
January 1996
ACS573MS
Radiation Hardened Octal
Three-State Transparent Latch
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96724 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
11
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability. . . . . . . . . . . >10
RAD (Si)/s, 20ns Pulse
12
RAD (Si)/s, 20ns Pulse
/mg
• Latch-Up Free Under Any Conditions
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
C to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay. . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
Description
The Intersil ACS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (
impedance state. The latch operation is independent of the state of
output enable.
The ACS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
LE) is High. When the latch goes low
OE) are high the output is in a high
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
1
OE
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
8
D6
9
D7
GND
10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
120
2
3
4
5
6
7
8
9
10
VCC
20
Q0
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
12
Q7
11
LE
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
5962F9672401VRC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP
5962F9672401VXC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack
ACS573D/Sample 25oC Sample 20 Lead SBDIP
ACS573K/Sample 25oC Sample 20 Lead Ceramic Flatpack
ACS573HMSR 25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number
518893
File Number 4093
Functional Diagram
Dn
ACS573MS
1 OF 8 IDENTICAL CIRCUITS
LE
p
n
LE
LE
p
n
LE
OE
VCC
p
Qn
OE
n
VSS
COMMON CONTROLS
LE
LE
OE
LE
OE OE
TRUTH TABLE
OE LE DATA OUTPUT
LHHH
LHLL
LLlL
LLhH
HXXZ
NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch
Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.
Spec Number 518893
2
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