Intersil Corporation ACS541MS Datasheet
January 1996
ACS541MS
Radiation Hardened Octal Buffer/
Line Driver Three-State
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96710 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
2
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
11
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability. . . . . . . . . . . >10
RAD (Si)/s, 20ns Pulse
12
RAD (Si)/s, 20ns Pulse
/mg
• Latch-Up Free Under Any Conditions
o
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
C to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay. . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
Description
The Intersil ACS541MS is a Radiation Hardened Octal Buffer/Line
Driver, with three-state outputs. The output enable pins
trol the Three-State outputs. If either enable is high the output will be in a
high impedance state. For data output both enables must be low.
The ACS541MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS541MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line package (D suffix).
OE1, OE2 con-
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
1
OE1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
8
A6
9
A7
GND
10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
120
2
3
4
5
6
7
8
9
10
VCC
20
OE2
19
Y0
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
13
12
Y6
Y7
11
19
18
17
16
15
14
13
12
11
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE
5962F9671001VRC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead SBDIP
5962F9671001VXC -55oC to +125oC MIL-PRF-38535 Class V 20 Lead Ceramic Flatpack
ACS541D/Sample 25oC Sample 20 Lead SBDIP
ACS541K/Sample 25oC Sample 20 Lead Ceramic Flatpack
ACS541HMSR 25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518856
File Number 4085
Functional Diagram
1
OE1
19
OE2
ACS541MS
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
18
Y0
17
Y1
16
Y2
15
Y3
14
Y4
13
Y5
8
A6
GND
VCC
10
20
A7
9
TRUTH TABLE
INPUTS OUTPUTS
OE1 OE2 An Yn
LLHH
LLLL
HXXZ
XHXZ
NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance
GND
VCC
GND
VCC
GND
12
Y6
11
Y7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518856
2
Loading...