Intersil Corporation ACS21MS Datasheet
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File Number 4757
ACS21MS
Radiation Hardened Dual 4-Input AND Gate
The Radiation Hardened ACS21MS is a Dual 4-Input AND
Gate. For each gate, a HIGH level on all inputs results in a
HIGH level on the Y output. A LOW level on any input
results in a LOW level on the Y output. All inputs are
buffered and the outputs are designed for balanced
propagation delay and transition times.
The ACS21MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS21MS are
contained in SMD 5962-98629. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/ne wsafc lasst.asp
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity. . . . . . . . . . . . .<1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
• Input Logic Levels. . . . V
IL
= (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . .5.0µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .15ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
ORDERING NUMBER
INTERNAL MARKETING
NUMBER TEMP. RANGE (oC) PACKAGE DESIGNATOR
5962F9862901VCC ACS21DMSR-03 -55 to 125 14 Ld SBDIP CDIP2-T14
ACS21D/SAMPLE-03 ACS21D/SAMPLE-03 25 14 Ld SBDIP CDIP2-T14
5962F9862901VXC ACS21KMSR-03 -55 to 125 14 Ld Flatpack CDFP3-F14
ACS21K/SAMPLE-03 ACS21K/SAMPLE-03 25 14 Ld Flatpack CDFP3-F14
5962F9862901V9A ACS21HMSR-03 25 Die NA
Pinouts
ACS21MS
(SBDIP)
TOP VIEW
ACS21MS
(FLATPACK)
TOP VIEW
A1
B1
NC
C1
D1
Y1
GND
V
CC
D2
C2
NC
B2
A2
Y2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1A1
B1
NC
C1
D1
Y1
GND
V
CC
D2
C2
NC
B2
A2
Y2
Data Sheet July 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at anytime without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howe ver, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Die Characteristics
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: AI
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
SUBSTRATE POTENTIAL
Unbiased Insulator
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
5
A/cm
2
Transistor Count: 92
Metallization Mask Layout
ACS21MS
B1 A1 V
CC
D2
NC
C1 (4)
NC
D1 (5)
(12) C2
NC
NC
(10) B2
(6) (7) (8) (9)
(2) (1)
(14)
(13)
A2Y2GNDY1
ACS21MS
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