Intersil Corporation ACS175MS Datasheet

ACS175MS

Data Sheet July 1999

Radiation Hardened Quad D-Type Flip­Flop with Reset

The Radiation Hardened ACS175MS is a Quad D-Type
Flip-Flop with Reset. Information at the D input is
transferred to the Q and
transition of the clock. All four flip-flops are controlled by a
common clock (CP) and acommonreset(
accomplished by a LOW level independent of the clock. All
inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.

The ACS175MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.

Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.

Detailed Electrical Specifications for the ACS175MS are
contained in SMD 5962-98635. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm

Q outputs on the positive-going

MR). Resetting is

File Number 4763

Features

• QML Qualified Per MIL-PRF-38535 Requirements

• 1.25 Micron Radiation Hardened SOS CMOS

• Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10

- SEU Immunity. . . . . . . . . . . . .<1 x 10

-10

5

RAD(Si)

Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm

• Input Logic Levels. . . . V

= (0.3)(VCC), VIH = (0.7)(VCC)

IL

• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)

• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .22ns (Max)

Applications

• High Speed Control Circuits

• Sensor Monitoring

• Low Power Designs

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)

Ordering Information

INTERNAL MARKETING

ORDERING NUMBER

5962F9863501VCC ACS175DMSR-03 -55 to 125 16 Ld SBDIP CDIP2-T16
ACS175D/SAMPLE-03 ACS175D/SAMPLE-03 25 16 Ld SBDIP CDIP2-T16
5962F9863501VXC ACS175KMSR-03 -55 to 125 16 Ld Flatpack CDFP4-F16
ACS175K/SAMPLE-03 ACS175K/SAMPLE-03 25 16 Ld Flatpack CDFP4-F16
5962F9863501V9A ACS175HMSR-03 25 Die NA

NUMBER TEMP. RANGE (oC) PACKAGE DESIGNATOR

Pinouts

MR

Q0
Q0
D0
D1
Q1
Q1

GND

ACS175MS

(SBDIP)

TOP VIEW

1
2
3
4
5
6
7
8

V

16

CC

15

Q3

14

Q3

13

D3

12

D2

11

Q2

10

Q2

9

CP

MR

Q0
Q0
D0
D1
Q1
Q1

GND

ACS175MS

(FLATPACK)

TOP VIEW

116
2
3
4
5
6
7
8

15
14
13
12
11
10

9

V
Q3
Q3
D3
D2
Q2
Q2
CP

CC

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Die Characteristics

ACS175MS

DIE DIMENSIONS:

Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)

METALLIZATION: AI

Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm

SUBSTRATE POTENTIAL

Unbiased Insulator

Metallization Mask Layout

Q0 (3)

PASSIVATION:

Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm

SPECIAL INSTRUCTIONS

Bond V

ADDITIONAL INFORMATION:

Worst Case Current Density: <2.0 x 10
Transistor Count: 280

ACS175MS

Q0 MR V
(2) (1) (16) (15)

CC

Q3

CC

First

(14)

Q3

5

A/cm

2

D0 (4)

D1 (5)

Q1 (6)

(7) (8) (9) (10)

Q2CPGNDQ1

(13) D3

(12) D2

(11)

Q2

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howe ver, no responsibility is assumed byIntersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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