Intersil Corporation ACS174MS Datasheet
ACS174MS
Data Sheet July 1999
Radiation Hardened Hex D-Type Flip-Flop
with Reset
The Radiation Hardened ACS174MS is a Hex D-Type FlipFlop with Reset. Information at the D input is transferred to
the Qoutput on the positive-going transition of the clock. All
six flip-flops are controlled by a common clock (CP) and a
common reset (
level independent of the clock. All inputs are buffered and
the outputs are designed for balanced propagation delay
and transition times.
The ACS174MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS174MS are
contained in SMD 5962-98634. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
MR). Resetting is accomplished by a LOW
File Number 4762
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
- SEU Immunity. . . . . . . . . . . . .<1 x 10
-10
5
RAD(Si)
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
• Input Logic Levels. . . . V
= (0.3)(VCC), VIH = (0.7)(VCC)
IL
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .23ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
2
)
Ordering Information
INTERNAL MARKETING
ORDERING NUMBER
5962F9863401VCC ACS174DMSR-03 -55 to 125 16 Ld SBDIP CDIP2-T16
ACS174D/SAMPLE-03 ACS174D/SAMPLE-03 25 16 Ld SBDIP CDIP2-T16
5962F9863401VXC ACS174KMSR-03 -55 to 125 16 Ld Flatpack CDFP4-F16
ACS174K/SAMPLE-03 ACS174K/SAMPLE-03 25 16 Ld Flatpack CDFP4-F16
5962F9863401V9A ACS174HMSR-03 25 Die NA
NUMBER TEMP. RANGE (oC) PACKAGE DESIGNATOR
Pinouts
MR
Q0
D0
D1
Q1
D2
Q2
GND
ACS174MS
(SBDIP)
TOP VIEW
1
2
3
4
5
6
7
8
16
V
CC
15
Q5
14
D5
13
D4
12
Q4
D3
11
10
Q3
9
CP
MR
Q0
D0
D1
Q1
D2
Q2
GND
ACS174MS
(FLATPACK)
TOP VIEW
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
V
Q5
D5
D4
Q4
D3
Q3
CP
CC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Die Characteristics
ACS174MS
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: AI
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
D0 (3)
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
Bond V
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
Transistor Count: 358
ACS174MSX
Q0 MR V
(2) (1) (16) (15)
CC
Q5
CC
First
(14) D5
5
A/cm
2
D1 (4)
Q1 (5)
D2 (6)
(7) (8) (9) (10)
Q3CPGNDQ2
(13) D4
(12) Q4
(11) D3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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