Intersil Corporation ACS132MS Datasheet
ACS132MS
Data Sheet November 1998 File Number 4546
Radiation Hardened Quad 2-Input NAND
Schmitt Trigger
The Radiation Hardened ACS132MS is a Quad 3-Input NAND
Gate with Schmitt Trigger inputs. When any input to one of the
gates is at a LOW lev el, the corresponding Y output will be
HIGH. A HIGH levelonbothinputswillcausetheoutputf orthat
gate to be LOW. The Schmitt Trigger input stage provides
400mV (Min)ofhysteresisand permitsinput signals with longer
rise times. All inputs are buffered and the outputs are designed
for balanced propagation delay and transition times .
The ACS132MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS132MS are
contained in SMD 5962-98625. A “hot-link” is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 10
- SEU Immunity. . . . . . . . . . . . <1 x 10
5
-10
RAD (Si)
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm
• Input Logic Levels . . . . V
= (0.3)(VCC), VIH = (0.7)(VCC)
IL
• Hysteresis Voltage . . . . . . . . . . . . . . . . . . . . 400mV (Min)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
2
)
Ordering Information
ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE (oC) PACKAGE DESIGNATOR
5962F9862501VCC ACS132DMSR-03 -55 to 125 14 Ld SBDIP CDIP2-T14
ACS132D/SAMPLE-03 ACS132D/SAMPLE-03 25 14 Ld SBDIP CDIP2-T14
5962F9862501VXC ACS132KMSR-03 -55 to 125 14 Ld Flatpack CDFP4-F14
ACS132K/SAMPLE-03 ACS132K/SAMPLE-03 25 14 Ld Flatpack CDFP4-F14
5962F9862501V9A ACS132HMSR-03 25 Die N/A
Pinouts
A1
B1
Y1
A2
B2
Y2
GND
ACS132MS
(SBDIP)
TOP VIEW
1
2
3
4
5
6
7
14
V
CC
B4
13
12
A4
Y4
11
B3
10
A3
9
Y3
8
B1
Y1
A2
B2
Y2
GND
ACS132MS
(FLATPACK)
TOP VIEW
1A1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
B4
A4
Y4
B3
A3
Y3
CC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Die Characteristics
ACS132MS
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ± 25µm (20.6 mils ± 1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: AL
Metal 1 Thickness: 0.7µm ± 0.1µm
Metal 2 Thickness: 1.0µm ± 0.1µm
SUBSTRATE POTENTIAL:
Unbiased Insulator
Metallization Mask Layout
Y1 (3)
ACS132MS
B1 A1 V
(2) (1)
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ± 0.15µm
SPECIAL INSTRUCTIONS:
CC
First
Bond V
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
Transistor Count: 92
B4
CC
(14)
(13)
(12) A4
5
A/cm
2
A2 (4)
NC
B2 (5)
(6) (7) (8) (9)
A3Y3GNDY2
(11) Y4
NC
(10) B3
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly ,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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