Intersil Corporation ACS109MS Datasheet
ACS109MS
Data Sheet July 1999
Radiation Hardened Dual J-K Flip-Flop
with Set and Reset
The Radiation Hardened ACS109MS is a Dual J-K FlipFlop with Set and Reset. These Flip-Flops have
independent J,
Q outputs. The outputs change state on the positive-going
transition of the clock. Set and Reset are accomplished
asynchronously by Low-level inputs. All inputs are buffered
and the outputs are designed for balanced propagation
delay and transition times.
The ACS109MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the DefenseSupply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS109MS are
contained in SMD 5962-98632. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/spaceselect.htm
K, Set, Reset, and Clock inputs and Q and
File Number 4760
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10
- SEU Immunity. . . . . . . . . . . . .<1 x 10
-10
5
RAD(Si)
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
• Input Logic Levels. . . . V
= (0.3)(VCC), VIH = (0.7)(VCC)
IL
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns (Max)
Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
2
)
Ordering Information
INTERNAL MARKETING
ORDERING NUMBER
5962F9863201VCC ACS109DMSR-03 -55 to 125 16 Ld SBDIP CDIP2-T16
ACS109D/SAMPLE-03 ACS109D/SAMPLE-03 25 16 Ld SBDIP CDIP2-T16
5962F9863201VXC ACS109KMSR-03 -55 to 125 16 Ld Flatpack CDFP4-F16
ACS109K/SAMPLE-03 ACS109K/SAMPLE-03 25 16 Ld Flatpack CDFP4-F16
5962F9863201V9A ACS109HMSR-03 25 Die NA
NUMBER TEMP. RANGE (oC) PACKAGE DESIGNATOR
Pinouts
1R
1K
1CP
1S
1Q
1Q
GND
1J
ACS109MS
(SBDIP)
TOP VIEW
1
2
3
4
5
6
7
8
16
V
CC
15
2R
14
2J
13
2K
12
2CP
11
2S
10
2Q
9
2Q
1R
1J
1K
1CP
1S
1Q
1Q
GND
ACS109MS
(FLATPACK)
TOP VIEW
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
V
CC
2R
2J
2K
2CP
2S
2Q
2Q
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Die Characteristics
ACS109MS
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: AI
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
1K (3)
ACS109MS
1J 1R
(2) (1)
PASSIVATION:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
CC
First
Bond V
ADDITIONAL INFORMATION:
Worst Case Current Density: <2.0 x 10
Transistor Count: 236
V
(16) (15)
CC
2R
(14) 2J
5
A/cm
2
(13)
1CP (4)
1S (5)
1Q (6)
(7) (8) (9) (10)
2QGND1Q
2Q
2K
(12) 2CP
2S
(11)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only .Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
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FAX: (321) 724-7240
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Republic of China
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FAX: (886) 2 2715 3029
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